TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 413

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

14.3.4
CODECRDY
ACRESET*
ENLINK
BITCLK
SYNC
SDIN
Boot up
ACLC internal clock becomes active
AC-link Start Up
signal to the link side (including AC-link). This bit defaults to ‘0’, so the CPU asserts the ACRESET*
signal when it boots up.
responsible for controlling the length of this period.
signal during the period from ACRESET* signal assertion to 162.8ns after ACRESET* signal
deassertion. ACLC assumes the primary CODEC meet this requirement.
the BITCLK signal is provided, ACLC starts the SYNC signal output, which indicates the start of the
AC-link frame, and starts the frame-length counting.
Ready” bit of the Tag slot. When ACLC detects that this bit has been set, the ACLC Interrupt Status
Register (ACINTSTS)’s CODEC[1:0] Ready (CODEC[1:0]RDY) bit is set. The system software is
able to recognize the readiness of the CODEC(s) by detecting this event by way of either polling or
interrupt.
connected to the SDIN1 signal of ACLC, the software must watch ACINTSTS.CODEC1RDY bit to
determine the CODEC’s readiness for the register access.
Figure 14.3.5 shows the conceptual sequence of AC-link start-up.
The ACLC Control Enable Register’s Enable AC-link bit is used to deassert/assert the ACRESET*
The AC’97 specification requires that the reset assertion period is 1µs or longer. The software is
The AC’97 specification also requires that the primary CODEC stops the AC-link clock (BITCLK)
Deasserting the link-side reset makes the primary CODEC start driving the BITCLK signal. When
When a CODEC becomes ready to receive access to its own register, the CODEC sets the “CODEC
In case of 5.1 channel audio connection example (Figure 14.3.2), because the secondary CODEC is
Figure 14.3.5 Cold Reset and CODEC Ready Recognition
Software sets ENLINK bit
Note: The number of BITCLK cycles relative to other signals is not to scale.
14-7
CODEC becomes ready to accept register access
Chapter 14 AC-link Controller