TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 226

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

9.3.4
(Channel Enable)
SDCCRn.CE
0
1
1
1
1
Initialization of Memory Data, ECC/Parity
channels. These functions are effective when quickly initializing data memory or ECC/parity memory.
(SDCCRn.ME) of the SDRAM Channel Control Register are set become the Master channel. Also,
channels for which both the Channel Enable bit (SDCCRn.CE) and the Slave Enable bit (SDCCRn.SE)
are set become the Slave channel. See Table 9.3.4 Master/Slave Channel Settings for information
regarding the Master/Slave channel settings.
Master channel are used when in the ECC/Parity mode. Please set to the same value the SDRAM
settings of all channels that are simultaneously written to.
access the Master channel. The DMAC has registers for setting memory initialization data. When the
DMAC is launched by an internal request when in the Single address IO→Memory Transfer mode, the
data set in this register are written to memory. See Chapter 8 "DMA Controller" for more information.
The SDRAMC has functions for simultaneously performing Memory Writes to multiple memory
Channels for which both the Channel Enable bit (SDCCRn.CE) and the Master Enable bit
The slave channel is simultaneously written to when the Master channel is written to. Settings of the
Using the DMA Controller and performing 32 double word Burst access is the most efficient way to
(Master Enable)
SDCCRn.ME
X
0
0
1
1
Table 9.3.4 Master/Slave Channel Settings
(Slave Enable)
SDCCRn.SE
X
0
1
0
1
9-10
Channel is disabled.
Normal operation is performed.
When a Write operation is executed by a channel
where SDCCRn.ME=1, the Write operation is also
executed by this channel.
Normal operation is performed when this channel is
Active.
When a Write operation is executed by this channel,
the Write operation is simultaneously executed by all
channels where SDCCRn.SE=1.
When a Write operation is executed by this channel,
the Write operation is simultaneously executed by all
channels where SDCCRn.SE=1.
A Write operation is also simultaneously executed by
this channel when the Write operation is executed by
another channel where SDCCRn.ME=1.
Chapter 9 SDRAM Controller
Description