TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 300

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

31:24
25:24
22:16
10:9
DPE
0x0
Bit
7:0
23
15
14
13
12
11
31
15
R
8
10.4.17 Satellite Mode PCI Status Register (PCISSTATUS)
Mnemonic
SSE
0x0
14
R
PMEEN
MDPE
RMA
DPE
SSE
RTA
STA
PS
DT
RMA
Space cannot be accessed when the PCI Controller is in the Satellite mode. It is possible however to
read values from either of these registers.
0x0
13
Reserved
R
The PCI Status, Command Register (PCISTATUS) or the PMCSR Register of the Configuration
Reserved
Power State
PME Enable
Reserved
Detected Parity
Error
Signaled System
Error
Received Master
Abort
Received Target
Abort
Signaled Target
Abort
Set DEVSEL
Timing
Data Parity
Detected
Reserved
RTA
0x0
Field Name
12
R
STA
0x0
11
R
Figure 10.4.15 Satellite Mode PCI Status Register
26
10
PowerState (Default: 0x0)
This is a shadow register of the PowerState field in the PMCSR Register.
Note: Read this field in the following procedures. If other procedures are
(1) General procedures
(2) Procedures to read at any time
PME_En (Default: 0x0)
This is a shadow register of the PME_En bit of the PMCSR Register.
Detected Parity Error (Default: 0x0)
This is a shadow register of the PCISTATUS.DPE bit.
Signaled System Error (Default: 0x0)
This is a shadow register of the PCISTATUS.SSE bit.
Received Master Abort (Default: 0x0)
This is a shadow register of the PCISTATUS.RMA bit.
Received Target Abort (Default: 0x0)
This is a shadow register of the PCISTATUS.RTA bit.
Signaled Target Abort (Default: 0x0)
This is a shadow register of the PCISTATUS.STA bit.
DEVSEL Timing (Fixed Value: 0x1)
This is a shadow register of the PCISTATUS.DT field.
Master Data Parity Error Detected (Default: 0x0)
This is a shadow register of the PCISTATUS.MDPE bit.
0x1
DT
R
After checking the P2GSTATUS.PMSC bit is set, read the PS field.
To read PS field directly, but not using the procedures shown above (1),
read the PS field twice consecutively. Use the value if the same value is
read.
25
used, incorrect data may be read.
9
0x0
PS
R
MDPE
0x0
24
R
8
10-42
PMEEN
0x0
23
R
7
22
Description
Chapter 10 PCI Controller
Reserved
0xD088
Reserved
Read/Write
R
R
R
R
R
R
R
R
R
16
0
⎯
⎯
⎯
: Type
: Initial value
: Type
: Initial value