TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 225

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

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The number of refresh operations can be counted using the refresh counter. With this function, it is no longer
necessary to assemble special timing groups in the software when counting refresh operations.
Setting the refresh cycle to a small value makes it possible to expedite completion of the refresh cycle required for
SDRAM initialization. As described above, please set normal values after the required number of refresh cycles have
been generated.
Refresh requests have priority over all other SDRAM Controller access requests. Please do not set the memory
refresh cycle to an unnecessarily short value.
9.3.3
Initialization of SDRAM
SDRAM. Using software to set each register makes it possible to execute initial settings at a particular
timing.
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The TX4937 Command Register has functions for generating the cycles required for initializing
Set the SDRAM Channel Control Register (SDCCRn).
Set the SDRAM Timing Register (SDCTR). This timing setting is applied to all channels, so please
set it to the slowest memory device.
Use the SDRAM Command Register (SDCCMD) to issue the Pre-charge All command.
Issue the Set Mode Register command in the same manner.
Set the refresh count required to initialize SDRAM to the refresh counter (SDCTR.RC)
refresh cycle (SDCTR.RP).
Wait until the refresh counter returns to “0.”
Set the refresh cycle (SDCTR.RP) to the proper value.
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Chapter 9 SDRAM Controller
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and set the