TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 420

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

14.3.7
14.3.6.7 Slot Activation Control
14.3.6.8 Variable Rate Limitation
GPIO Operation
Register (ACGPODAT) in the following way:
•
•
ACLC supports the slot 12 for the MC’97 (Modem Codec) GPIO.
The slot 12 is shadowed in the ACLC GPI Data Register (ACGPIDAT) and ACLC GPO Data
This shadowing function is enabled as long as ACSLTEN allows.
The bit 0 of the slot 12 is defined as ‘GPIO_INT’ and can cause ACLC to request an interrupt.
ACLC copies the slot 12 input data into the ACGPIDAT register, if the slot 12 input is marked by
the CODEC as valid in the AC-link frame period.
ACLC generates the slot 12 output data from the ACGPODAT register and mark it as valid, if the
slot 12 is required from the CODEC in the previous AC-link frame.
time, slot activation control will be useful. To use this feature, the software must deactivate the
relevant streams first, enable ACLC Control Enable Register (ACCTLEN), make sure the
transmission FIFO becomes full by checking ACLC FIFO Status Register (ACFIFOSTS)’s Full
(xxxxFULL) bit, and finally enable ACLC Slot Enable Register (ACSLTEN). This procedure
assures that all the reception streams are activated at a frame and all the transmission streams
begin to respond to the slot-request bits of that frame.
to synchronize with the link-side. Refer to the register description for detail.
most usages, the initial ACSLTEN value enables all the transmission and reception through the
slots by default.
combines sample-data for the slots 3 and 4 into one DMA channel, and similarly for the slots 7
and 8. This feature effectively considers that the slot request bit from the CODEC for slot 4 shall
be always same (in tandem) as for slot 3 for each frame, and similarly for the slots 7 and 8. ACLC
also considers that the slot valid bit from the CODEC for slot 4 shall be always same (in tandem)
as for slot 3 for each frame.
In case ACLC is required to begin transmission or reception of multiple streams at the same
Note that access to ACSLTEN and ACLC Slot Disable Register (ACSLTDIS) needs special care
Since operating ACCTLEN register and DMAC without touching ACSLTEN is sufficient for
To improve compatibility with existing AC’97 CODECs and controllers on the market, ACLC
14-14
Chapter 14 AC-link Controller