TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 367

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

11.3.4
11.3.5
11.3.6
Data Reception
to “0”, reception operation starts after the RXD signal start bit is detected. Start bits are detected when
the RXD signal transitions from the High state to the Low state. Therefore, the RXD signal is not
interpreted as a start bit if it is Low when the Serial Data Reception Disable bit is set to “0”.
DMA/Interrupt Status Register (SIDISRn) is set if the byte count of the stored reception data exceeds
the value set by the Receive FIFO Request Trigger Level field (RDIL) of the FIFO Control Register
(SIFCRn).
Control Register (SIDICRn) is set. The received data can be read from the Receive FIFO Data Register
(SIRFIFOn).
DMA/Interrupt Control Register (SIDICRn) is set.
Data Transmission
Disable bit (TSDE) of the Flow Control Register (SIFLCRn) is set to “0”.
Transmit FIFO Request Trigger Level (TDIL) of the Control Register (SIFCRn), the transmission data
empty bit (TDIS) of the DMA/Interrupt Status Register (SIDISRn) is set.
Control Register (SIDICRn) is set.
DMA/Interrupt Control Register (SIDICRn) is set.
DMA Transfer
used to allocate DMA channels for each reception and transmission channel in the following manner.
When the Serial Data Reception Disable bit (RSDE) of the Flow Control Register (SIFLCRn) is set
The received data are stored in the Receive FIFO. The Reception Data Full bit (RDIS) of the
An interrupt is signaled when the Reception Data Interrupt Enable bit (RIE) of the DMA/Interrupt
In addition, DMA transfer is initiated when the Reception Data DMA Enable bit (RDE) of the
Data stored in the Transmission Data FIFO are transmitted when the Serial Data Transmission
If the available space in the Transmit FIFO is equal to or greater than the byte count set by the
An interrupt is signaled when the Transmission Data Interrupt Enable bit (TIE) of the DMA/Interrupt
In addition, DMA transfer is initiated when the Transmission Data DMA Enable bit (TDE) of the
The DMA Request Select field (INTDMA[7:0]) of the Pin Configuration Register (PCFG) can be
Set the DMA Channel Control Register of the DMA Controller as described below.
SIO Channel 1 Reception
SIO Channel 1 Transmission
SIO Channel 0 Reception
SIO Channel 0 Transmission
DMA Request Polarity
DMA Acknowledge Polarity
Request Detection
DMA Channel 0
DMA Channel 1
DMA Channel 2
DMA Channel 3
Low Active
Low Active
Level Detection
11-7
Chapter 11 Serial I/O Port
DMCCRn.REQPOL = 0
DMCCRn.EGREQ = 0
DMCCRn.ACKPOL = 0