TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 301

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

DPEIE SSEIE RMAIE RTAIE STAIE
31:16
10:9
R/W
0x0
Bit
7:0
15
14
13
12
11
13
12
11
31
15
8
10.4.18 PCI Status Interrupt Mask Register (PCIMASK) 0xD08C
Mnemonic
R/W
0x0
14
MDPEIE
RMAIE
DPEIE
SSEIE
RTAIE
STAIE
RMA
RTA
STA
R/W
0x0
13
Reserved
Detected Parity
Error Interrupt
Enable
Signaled System
Error Interrupt
Enable
Received Master
Abort Interrupt
Enable
Received Target
Abort Interrupt
Enable
Signaled Target
Abort Interrupt
Enable
Received Master
Abort
Received Target
Abort
Signaled Target
Abort
Reseved
Master Data
Parity Detected
Interrupt Enable
Reserved
R/W
0x0
Field Name
12
R/W
0x0
11
Figure 10.4.16 PCI Status Interrupt Mask Register
10
Reserved
Detected Parity Error Interrupt Enable (Default: 0x0)
Generates an interrupt when a parity error is detected.
Usually, this interrupt is masked and a Master Data Parity error signals the
error to the system.
1: Generates an interrupt.
0: Does not generate an interrupt.
Signaled System Error Interrupt Enable (Default: 0x0)
Generates an interrupt when a system error is signaled.
1: Generates an interrupt.
0: Does not generate an interrupt.
Received Master Abort Interrupt Enable (Default: 0x0)
Generates an interrupt when a Master Abort is received.
1: Generates an interrupt.
0: Does not generate an interrupt.
Received Target Abort Interrupt Enable (Default: 0x0)
Generates an interrupt when a Target Abort is received.
1: Generates an interrupt.
0: Does not generate an interrupt.
Signaled Target Abort Interrupt Enable (Default: 0x0)
Generates an interrupt when a Target Abort is signaled.
1: Generates an interrupt.
0: Does not generate an interrupt.
Received Master Abort (Default: 0x0)
This is a shadow register of the PCISTATUS.RMA bit.
Received Target Abort (Default: 0x0)
This is a shadow register of the PCISTATUS.RTA bit.
Signaled Target Abort (Default: 0x0)
This is a shadow register of the PCISTATUS.STA bit.
Master Data Parity Detected Interrupt Enable (Default: 0x0)
Generates an interrupt when data parity is detected.
1: Generates an interrupt.
0: Does not generate an interrupt.
9
MDPEIE
R/W
0x0
Reserved
8
10-43
7
Description
Chapter 10 PCI Controller
Reserved
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
16
0
⎯
⎯
⎯
: Type
: Initial value
: Type
: Initial value