TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 453

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

15.3.5
15.3.6
(Internal Timer Interrupts: Invalid)
(Internal Timer Interrupts: Valid)
Interrupt notification
Interrupt Current Status Register (IRCS) and an interrupt is reported to the TX49/H3 core.
The interrupt notification from the Interrupt Controller is reflected in the IP[2] bit. The Interrupt
Handler uses the IP[2] bit to judge whether or not there are interrupts from this Interrupt Controller and
uses the Interrupt Current Status Register (IRCS) to determine the interrupt cause.
Since bit IP[7] is also being used for notification of TX49/H3 CPU core internal timer interrupts, the
contents specified by IP[7] differ according to whether internal timer interrupts are set to valid
(TINTDIS=0) or invalid (TINTDIS=1), as indicated Table 15.3.3.
See the explanation “3.3 Configuration Signals” for more information.
Clearing interrupt requests
•
•
When the interrupt with the highest priority is selected, then the interrupt factor is reported to the
The TX49/H3 core distinguishes interrupt factors using the IP field (IP[7:2]) of the Cause Register.
The Interrupt Factor field (IRCS.CAUSE) value is reflected in the remaining bits of the IP field.
TINTDIS is the value that is set from DATA[7] at the timing when the RESET* signal is deasserted.
Interrupt requests are cleared according to the following process.
When the detection mode is set to the High level or Low level:
Operation is performed to deassert the request of a source that is asserting an interrupt request.
When the detection mode is set to Rising edge or Falling edge
Edge detection requests are cleared by first specifying the interrupt source of the interrupt request
to be cleared in the Edge Detection Clear Source field (EDCS0 or EDCS1) of the Interrupt Edge
Detection Clear Register (IREDC) then writing the resulting value when the corresponding Edge
Detection Clear Enable bit (EDCE0 or EDCE1) is set to “1.”
Table 15.3.3 Interrupt Notification to IP[7:2] of the CP0 Cause Register
TINTDIS
0
1
Interrupt Notification
Internal Timer
IP[7]
15-7
IRCS.CAUSE[4:0]
Chapter 15 Interrupt Controller
IRCS.CAUSE[3:0]
IP[6:3]
IRCS.IF
IRCS.IF
IP[2]