TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 380

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

SWRST
31:16
R/W
14:9
Bit
8:7
6:5
4:3
31
15
15
0
2
1
0
11.4.5
Mnemonic
14
SWRST
RFRST
FRSTE
TFRST
RDIL
TDIL
⎯
⎯
⎯
These registers set control of the Transmit/Receive FIFO buffer.
FIFO Control Register 0 (SIFCR0)
FIFO Control Register 1 (SIFCR1)
Reserved
Software Reset
Reserved
Receive FIFO
Request Trigger
Level
Reserved
Transmit FIFO
Request Trigger
Level
Transmit FIFO
Reset
Receive FIFO
Reset
FIFO Reset
Enable
Reserved
Field Name
Software Reset (Default: 0)
This field performs SIO resets except for the FIFOs. Setting this bit to “1”
initiates the reset. Set registers are also initialized. This bit returns to “0”
when initialization is complete.
0: Normal operation
1: SIO software reset
Receive FIFO DMA/Interrupt Trigger Level (Default: 00)
This register sets the level for reception data transfer from the Receive
FIFO.
00: 1 Byte
01: 4 Bytes
10: 8 Bytes
11: 12 Bytes
Transmit FIFO DMA/Interrupt Trigger Level (Default: 00)
This register sets the level for transmission data transfer to the Transmit
FIFO.
00: 1 Byte
01: 4 Bytes
10: 8 Bytes
11: Setting disabled
Transmit FIFO Reset (Default: 0)
The Transmit FIFO buffer is reset when this bit is set. This bit is valid when
the FIFO Reset Enable bit (FRSTE) is set. Cancel reset by using the
software to clear this bit.
0: During operation
1: Reset Transmit FIFO
Receive FIFO Reset (Default: 0)
The Receive FIFO buffer is reset when this bit is set. This bit is valid when
the FIFO Reset Enable bit (FRSTE) is set. Cancel reset by using the
software to clear this bit.
0: During operation
1: Reset Receive FIFO
FIFO Reset Enable (Default: 0)
This field is the Reset Enable for the Transmit/Receive FIFO buffer. The
FIFO is reset by combining the Transmit FIFO Reset bit (TFRST) and
Receive FIFO Reset bit (RFRST).
0: During operation
1: Reset Enable
Figure 11.4.5 FIFO Control Register
9
Reserved
8
RDIL
R/W
00
11-20
7
0xF310 (Ch. 0)
0xF410 (Ch. 1)
Reserved
6
Description
⎯
⎯
⎯
5
Chapter 11 Serial I/O Port
4
TDIL
R/W
00
3
TFRST RFRST FRSTE
R/W
2
0
R/W
1
0
R/W : Type
Read/Write
16
R/W
R/W
R/W
R/W
R/W
R/W
0
0
⎯
⎯
⎯
: Type
: Initial value
: Initial value