TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 91

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

63:27
63
47
31
15
Bit
26
25
24
23
22
21
20
19
18
5.2.5
Mnemonic
DMA1CKD
DMA0CKD
TM0CKD
TM1CKD
TM2CKD
ACLCKD
PIOCKD
PCICKD
Reserved
⎯
⎯
Clock Control Register (CLKCTR)
modules out of the reset state, the corresponding bits must be cleared by software. Before clearing them,
wait at least 128 CPU clock cycles after they are set.
Bit 32 and bits 15-0 are reset bits for the on-chip peripheral modules. To bring on-chip peripheral
Reserved
DMAC1 Clock
Disable
ACLC Clock
Disable
PIO Clock
Disable
DMAC0 Clock
Disable
PCIC Clock
Disable
Timer 0 Clock
Disable
Timer 1 Clock
Disable
Timer 2 Clock
Disable
Field Name
⎯
DMA1CKD
DMA1RST
R/W
R/W
26
10
0
0
Figure 5.2.5 Clock Control Register (1/2)
Controls clock pulses for the DMA controller 1.
0 = Supply clock pulses.
1 = Do not supply clock pulses.
Controls clock pulses for the AC-link controller.
0 = Supply clock pulses.
1 = Do not supply clock pulses.
Controls clock pulses for the parallel IO controller.
0 = Supply clock pulses.
1 = Do not supply clock pulses.
Controls clock pulses for the DMA controller 0.
0 = Supply clock pulses.
1 = Do not supply clock pulses.
Controls clock pulses for the PCI controller.
0 = Supply clock pulses.
1 = Do not supply clock pulses.
Always set this bit to 1.
Controls clock pulses for the TMR0 controller.
0 = Supply clock pulses.
1 = Do not supply clock pulses.
Controls clock pulses for the TMR1 controller.
0 = Supply clock pulses.
1 = Do not supply clock pulses.
Controls clock pulses for the TMR2 controller.
0 = Supply clock pulses.
1 = Do not supply clock pulses.
ACLCKD PIOCKD DMACKD PCICCKD
ACLRST
R/W
R/W
25
0
9
0
PIORST
R/W
R/W
24
Reserved
Reserved
0
8
0
DMA0RST
R/W
R/W
5-11
23
0
7
0
Description
PCICRST
R/W
R/W
⎯
Chapter 5 Configuration Registers
22
0
6
0
R/W
R/W
21
5
1
1
1
1
0xE020
TM0CKD TM1CKD TM2CKD SIO0CKD SIO1CKD
TM0RST TM1RST TM2RST SIO0RST SIO1RST
R/W
R/W
20
0
4
0
R/W
R/W
19
0
3
0
R/W
R/W
18
0
2
0
Initial Value Read/Write
0
0
0
0
0
1
0
0
0
⎯
R/W
R/W
17
0
1
0
R/W : Type
R/W : Type
48
32
16
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
: Type
: Initial value
: Type
: Initial value
: Initial value
: Initial value
⎯