TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 270

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

Memory Space 0
Memory Space 1
Memory Space 2
I/O Space
10.3.6
10.3.7
Swap (see10.3.7). Table 10.3.5 shows the settings registers for these properties.
set by the Target Pre-fetch Read Burst Length Field (P2GCFG.TPRBL) of the P2G Configuration
Register during a PCI target Read transaction. This is performed using accesses to resources that will
not be affected even if a pre-read such as memory is performed. Also, PCI Burst Reads to memory
spaces that were set to I/O space and pre-fetch disable are not supported.
Post Write Function
transaction without waiting for the other bus to complete its transaction when the first bus issues a Write
transaction. Initiator Write can Post Write a maximum of four Write transactions, and Target Write can
Post Write a maximum of nine Write transactions.
with Initiator Configuration Write and Target I/O Write is not recognized. However, the TX4937 PCI
Controller can even perform Post Writes to these functions. In order to guarantee that these Writes are
completed by the target device, please execute Reads to the device that performed the Write, then either
refer to the read value (so the TX49/H3 core can support non-blocking load) or execute the SYNC
instruction.
Endian Switching Function
PCI Bus is only defined in Little Endian logic. Therefore, when the TX4937 is in the Big Endian mode,
either the software or the hardware must perform some kind of conversion when exchanging data larger
than 2 B in size with the PCI Bus.
the DWORD (32-bit) data for each access window.
Note: Always use PCI single reads. Don’t use burst reads.
It is possible to set each space to valid/invalid, pre-fetch Read to valid/invalid, or to perform Word
When pre-fetch Reads are set to valid, data transfer is performed on the G-Bus according to the size
The Post Write function improves system performance by completing the original bus Write
Due to compatibility issues with old PC software in the PCI specifications, performing Post Writes
The TX4937 supports both the Little Endian mode and the Bit Endian mode. On the other hand, the
The PCI Controller can specify the endian switching function that reverses the byte arrangement of
MemEnable:
IOEnable:
PCICCFG.TCAR & MemEnable &
P2GM0GBASE.P2GM0EN
PCICCFG.TCAR & MemEnable &
P2GM1GBASE.P2GM1EN
PCICCFG.TCAR & MemEnable &
P2GM2GBASE.P2GM2EN
PCICCFG.TCAR & IOEnable &
P2GIOGBASE.P2GIOEN
Host mode:
Satellite mode: Command Register Memory Space bit
Host mode:
Satellite mode: Command Register I/O Space bit
Table 10.3.5 Target Access Space Properties Register
Enable
PCI State Command Register Memory Space bit (PCISTATUS.MEMSP)
PCI State Command Register I/O Space bit (PCISTATUS.IOSP)
P2GCFG.MEM0PD (valid)
P2GCFG.MEM1PD (valid)
P2GCFG.MEM2PD (invalid)
Always invalid
10-12
Pre-fetch (Initial State)
Chapter 10 PCI Controller
P2GM0GBASE.BSWAP
P2GM1GBASE.BSWAP
P2GM2GBASE.BSWAP
P2GIOGBASE.BSWAP
Word Swap