TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 64
TMPR4937XBG-300
Manufacturer Part Number
TMPR4937XBG-300
Description
Manufacturer
Toshiba
Datasheet
1.TMPR4937XBG-300.pdf
(552 pages)
Specifications of TMPR4937XBG-300
Family Name
TX49
Device Core Size
64b
Frequency (max)
300MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.5V
Operating Supply Voltage (max)
1.6V
Operating Supply Voltage (min)
1.4V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
BGA
Lead Free Status / Rohs Status
Compliant
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3.2
PCI controller
Peripheral
External bus
Function
controller
Boot Configuration
various functions upon booting the system. The states of the configuration signals immediately after the
RESET* or CGRESET* signal is deasserted are read as initial values for the TX4937 internal registers. A
High signal level sets a value of 1 and a Low signal level sets a value of 0.
corresponding pin on the board using an approx. 4.7 kΩ resistor. Driving a signal High does not require a
pull-down resistor. Any signals defined as Reserved should not be pulled down.
describe each configuration signal.
Others
Clock
The ADDR[19:0] and DATA[15:0] signals can also function as configuration signals for initially setting
All configuration signals are provided with internal pull-up resistors. To drive a signal Low, pull down the
Table 3.2.1 lists the functions that can be set using configuration signals. Table 3.2.2 and Table 3.2.3
Table 3.2.1 Functions that Can be Set Using Configuration Signals
PCI controller operating mode (satellite or host)
Division ratio of PCICLK[5:0] to CPUCLK
PCI bus arbiter selection (internal or external)
Division ratio of SYSCLK to GBUSCLK
Boot device selection
Division ratio of the external bus controller clock upon booting
BE[3:0]*/BWE[3:0]* function selection upon booting
Handling of the ACK signal upon booting (internal or external)
Data bus width for the boot device
Division ratio of CPUCLK to MASTERCLK
Shared pin function setting
Endian setting
Board information setting
Controlling built-in timer interrupts of the TX49/H3 core
Functions that Can be Set
3-10
Chapter 3 Signals
ADDR[19]
ADDR[11:10]
DATA[2]
ADDR[14:13]
ADDR[8:6]
DATA[5]
DATA[4]
DATA[1:0]
ADDR[3:0]
ADDR[18], ADDR[9]
DATA[6], DATA[3]
ADDR[12]
DATA[15:8]
DATA[7]
Configuration
Signal
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