TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 241

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

63:28
26:24
23:22
20:16
63
47
31
15
—
—
—
—
15:8
Bit
7:2
27
21
1
0
9.4.5
Mnemonic
—
—
—
—
ERRMODE
ERRAD
ERRMW
ERRAD
MBERR
SBERR
ERRS
R
—
—
—
—
—
—
—
—
ECC Status Register (ECCSR)
Error Address
Error ECC/Parity
Mode
Error Memory
Width
Error Syndrome
Multi-Bit Error
Single-Bit Error
—
28
—
—
—
Field Name
ERRS
R
Reserved
—
—
—
—
27
—
—
—
26
—
—
—
—
ERRMODE
Error Address (Default: Unknown)
A 36-bit physical address is set when an error occurs. This address is
retained until either SBERR or MBERR is cleared. This field is Read Only.
Reserved
Error ECC Mode (Default: Unknown)
The ECC/Parity Mode is set when an error occurs. This address is retained
until either SBERR or MBERR is cleared. This field is Read Only.
Reserved
Error Memory Width (Default: Unknown)
The memory data width is set when an error occurs. This address is
retained until either SBERR or MBERR is cleared. This field is Read Only.
0: 64 bits
1: 32 bits
Reserved
Error Syndrome (Default: Unknown)
The error syndrome for when errors occur is set. The syndrome is retained
until either SBERR or MBERR is cleared. This field is Read Only.
Reserved
Multi-Bit Error (Default: 0)
This bit is set to “1” when a multi-bit error occurs, or when a parity error
occurs while in the Parity Mode. Once a multi-bit error occurs, until this bit
is cleared, no status in the Status Register is updated even if new multi-
/single-bit errors occur.
0: No error
1: Generate error
Single-Bit Error (Default: 0)
This bit is set to “1” when a single-bit error occurs. Once a single-bit error
occurs, until this bit is cleared, no status in the Status Register is updated
even if new single-bit error occurs. If a multi-bit error occurs, status is
updated regardless of whether a single-bit error has occurred or not.
0: No error
1: Generate error
Figure 9.4.5 ECC Status Register
—
—
—
—
R
—
24
—
—
—
8
ERRAD
ERRAD
R
R
9-25
23
—
—
—
Reserved
7
—
22
—
—
Description
ERRMW
Chapter 9 SDRAM Controller
—
21
—
—
Reserved
R
0xA008
—
20
—
—
—
Reserved
—
—
2
MBERR SBERR
R/W
—
—
1
0
R/W :Type
48
—
32
—
16
Read/Write
0
0
R
R
R
R
R/W
R/W
:Type
:Initial value
:Type
:Initial value
:Type
:Initial value
:Initial value
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