TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 501

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

20.2.2
20.2.3
MSB
7
00000100 - 00001111
00010001 - 01111111
10000000 - 11111110
except for power supply, TDI, TCK, TDO, TMS, TRST*, and TEST[4]* are connected. Figure 20.2.3 shows
the bits of the Boundary Scan Register.
Significant Bit (LSB) of the Boundary Scan Register is sent from the TDO output.
Instruction Code
11111111 (0xFF)
00000000 (0x00)
00000001 (0x01)
00000010 (0x02)
00000011 (0x03)
00010000 (0x10)
The Boundary Scan Register contains a single 391-bit shift register to which all TX4937 I/O signals
TDI input is fetched to the Most Significant Bit (MSB) of the Boundary Scan Register and the Least
Table 20.2.2 shows the boundary scan sequence relative to the processor signals.
MSB → LSB
Instruction Register
either one or both of the test to be performed and the Test Data Register to be accessed. The Data
Register is selected according to the instruction code in Table 20.2.1. Refer to the “64-bit TX System
RISC TX49/H2, TX49/H3, TX49/H4 Core Architecture” for more information regarding each
instruction.
Boundary Scan Register
390
The JTAG Instruction Register consists of an 8-bit shift register. This register is used for selecting
Figure 20.2.1 shows the format of the Instruction Register.
The instruction code is shifted to the Instruction Register starting from the Least Significant Bit.
TDI
6
Table 20.2.1 Bit Configuration of JTAG Instruction Register
Figure 20.2.2 Shift Direction of the Instruction Register
Refer to the “64-bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core Architecture”
MSB
5
Figure 20.2.3 Boundary Scan Register
Figure 20.2.1 Instruction Register
SAMPLE/PRELOAD
Refer to TX4937 BSDL file
Instruction
Reserved
Reserved
Reserved
BYPASS
EXTEST
IDCODE
HIGHZ
4
20-3
Chapter 20 Extended EJTAG Interface
3
LSB
2
Selected Data Register
Boundary Scan Register
Boundary Scan Register
Device ID Register
Bypass Register
Bypass Register
Reserved
Reserved
Reserved
1
TDO
0
LSB
0