TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 166

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

(DMCCRn.XFSZ)
1 Byte
2 Bytes
4 Bytes
8 Bytes
4 Double Words
8 Double Words
16 Double Words
32 Double Words
Transfer Setting
8.3.7.1
Size
Table 8.3.2 Channel Register Setting Restrictions During Single Address Transfer
Channel Register Settings During Single Address Transfer
these restrictions are not met, then a Configuration Error is detected, the Configuration Error bit
(CFERR) of the DMA Channel Status Register (DMCSRn) is set and DMA transfer is not
performed.
(DMSAIRn). Setting 0 is only possible during transfer from memory to external I/O. A
Configuration Error will result if the value “0” is set during transfer from external I/O to memory
or during Memory Fill transfer.
transfer setting size is 2 bytes or larger, then set the DMA Source Address Register (DMSARn)
with 1 to 3 low-order bits complemented.
•
•
•
•
•
Destination Address Increment Register (DMDAIRn) settings are ignored.
Table 8.3.2 shows restrictions of the Channel Register settings during Single Address transfer. If
For Burst transfer, +8, 0, or –8 can be set to the DMA Source Address Increment Register
If the setting of the DMA Source Address Increment Register (DMSAIRn) is negative and the
During Single Address transfer, the DMA Destination Address Register (DMDARn) and DMA
If the transfer size is 2 bytes, set the DMSARn with the low-order 1 bit complemented.
If the transfer size is 4 bytes, set the DMSARn with the low-order 2 bits complemented.
If the transfer size is 8 bytes or larger, set the DMSARn with the low-order 3 bits
complemented.
DMSAIRn setting is “0” or greater: 0x0_0001_0000
DMSAIRn setting is a negative value: 0x0_0001_0007
DMSAIRn is “0” or
Example: When the transfer address is 0x0_0001_0000, the DMA Source Address
greater
000
000
*00
***
**0
Register (DMSARn) is as follows below.
DMSARn[2:0]
DMSAIRn setting is a
negative value
8-10
*00
111
111
***
**0
Chapter 8 DMA Controller
DMSAIRn[2:0]
8/0/-8
*00
000
***
**0
DMCNTRn[2:0]
*00
000
000
**0
***