TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 168

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

8.3.8
8.3.8.1
Dual Address Transfer
applies to the following DMA transfer modes.
This section explains the register settings for Dual Address transfer (DMCCRn.SNGAD = 0). This
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Channel Register Settings During Dual Address Transfer
these restrictions are not met, then a Configuration Error is detected, the Configuration Error bit
(CFERR) of the DMA Channel Status Register (DMCSRn) is set, and DMA transfer is not
performed.
transfer setting size is 8 bytes or larger, then a value will be set in the DMA Source Address
Register (DMSARn) that reflects as follows.
transfer size is 2 bytes or larger, set the DMA Source Address Register (DMSARn) as follows:
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negative and the transfer size is 2 bytes or larger, set the DMA Destination Address Register
(DMDARn) as follows:
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Table 8.3.3 shows restrictions of the Channel Register settings during Dual Address transfer. If
If the setting of the DMA Source Address Increment Register (DMSAIRn) is negative and the
If the setting of the DMA Source Address Increment Register (DMSAIRn) is negative and the
Likewise, if the setting of the DMA Destination Address Increment Register (DMDAIRn) is
External I/O (Dual Address) transfer
Internal I/O DMA transfer
Memory-Memory Copy transfer
If the transfer size is 2 bytes, set the DMSARn with the low-order 1 bit complemented.
If the transfer size is 4 bytes, set the DMSARn with the low-order 2 bits complemented.
If the transfer size is 8 bytes or larger, set the DMSARn with the low-order 3 bits
complemented.
If the transfer size is 2 bytes, set the DMDARn with the low-order 1 bit complemented.
If the transfer size is 4 bytes, set the DMDARn with the low-order 2 bits complemented.
If the transfer size is 8 bytes or larger, set the DMDARn with the low-order 3 bits
complemented.
DMSAIRn setting is “0” or greater: 0x0_0001_0000
DMSAIRn setting is a negative value: 0x0_0001_0007
Example: When the transfer address is 0x0_0001_0000, the DMA Source Address
Register (DMSARn) is as follows below.
8-12
Chapter 8 DMA Controller