SAM3A4C Atmel Corporation, SAM3A4C Datasheet - Page 1085

• Manufacturer Part Number: SAM3A4C
• Manufacturer: Atmel Corporation

39.5.2.11
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Special considerations for control endpoints
STALL handshake and retry mechanism
Overview
Control write
Management of Control Endpoints
Each time a STALL handshake is sent, the UOTGHS_DEVEPTISRx.STALLEDI bit is set by the
UOTGHS and the PEP_x interrupt is set.
If a SETUP packet is received into a control endpoint for which a STALL is requested, the
R e c e i v e d S E T U P I n t e r r u p t ( U O T G H S _ D E V E P T I S R x . R X S T P I ) b i t i s s e t a n d
UOTGHS_DEVEPTIMRx.STALLRQ and UOTGHS_DEVEPTISRx.STALLEDI are cleared. The
SETUP has to be ACKed.
This simplifies the enumeration process management. If a command is not supported or con-
tains an error, the user requests a STALL and can return to the main task, waiting for the next
SETUP request.
The retry mechanism has priority over the STALL handshake. A STALL handshake is sent if the
UOTGHS_DEVEPTIMRx.STALLRQ bit is set and if no retry is required.
A SETUP request is always ACKed. When a new SETUP packet is received, the
U O T G H S _ D E V E P T I S R x . R X S T P I i s s e t ; t h e R e c e i v e d O U T D a t a I n t e r r u p t
(UOTGHS_DEVEPTISRx.RXOUTI) bit is not.
The FIFO Control (UOTGHS_DEVEPTIMRx.FIFOCON) bit and the Read-write Allowed
(UOTGHS_DEVEPTISRx.RWALL) bit are irrelevant for control endpoints. The user shall never
use them on these endpoints. When read, their values are always zero.
Control endpoints are managed using:
Figure 39-14 on page 1086
troller will not necessarily send a NAK on the first IN token:
• the UOTGHS_DEVEPTISRx.RXSTPI bit, which is set when a new SETUP packet is received
• the UOTGHS_DEVEPTISRx.RXOUTI bit, which is set when a new OUT packet is received
• the Transmitted IN Data Interrupt (UOTGHS_DEVEPTISRx.TXINI) bit, which is set when the
• if the user knows the exact number of descriptor bytes that must be read, it can then
• it can read the bytes and wait for the NAKed IN Interrupt (UOTGHS_DEVEPTISRx.NAKINI),
and which shall be cleared by firmware to acknowledge the packet and to free the bank;
and which shall be cleared by firmware to acknowledge the packet and to free the bank;
current bank is ready to accept a new IN packet and which shall be cleared by firmware to
send the packet.
anticipate the status stage and send a zero-length packet after the next IN token, or
which tells that all the bytes have been sent by the host and that the transaction is now in the
status stage.
shows a control write transaction. During the status stage, the con-
SAM3X/A
SAM3X/A
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