SAM3A4C Atmel Corporation, SAM3A4C Datasheet - Page 1088

• Manufacturer Part Number: SAM3A4C
• Manufacturer: Atmel Corporation

Figure 39-17. Example of an IN Endpoint with 2 Data Banks
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UOTGHS_DEVEPTIMRx. FIFOCON
Detailed description
UOTGHS_DEVEPTISRx. TXINI
SAM3X/A
SAM3X/A
The data is written, following the next flow:
If the endpoint uses several banks, the current one can be written while the previous one is
being read by the host. Then, when the user clears UOTGHS_DEVEPTIMRx.FIFOCON, the fol-
lowing bank may already be free and UOTGHS_DEVEPTISRx.TXINI is set immediately.
An “Abort” stage can be produced when a zero-length OUT packet is received during an IN
s t a g e o f a c o n t r o l o r i s o c h r o n o u s I N t r a n s a c t i o n . T h e K i l l I N B a n k
(UOTGHS_DEVEPTIMRx.KILLBK) bit is used to kill the last written bank. The best way to man-
age this abort is to apply the algorithm represented on
• When the bank is empty, UOTGHS_DEVEPTISRx.TXINI and
• The user acknowledges the interrupt by clearing UOTGHS_DEVEPTISRx.TXINI.
• The user writes the data into the current bank by using the USB Pipe/Endpoint nFIFO Data
• The user allows the controller to send the bank and switches to the next bank (if any) by
UOTGHS_DEVEPTIMRx.FIFOCON are set, which triggers a PEP_x interrupt if
UOTGHS_DEVEPTIMRx.TXINE is one.
(USBFIFOnDATA) register, until all the data frame is written or the bank is full (in which case
UOTGHS_DEVEPTISRx.RWALL is cleared and the Byte Count
(UOTGHS_DEVEPTISRx.BYCT) field reaches the endpoint size).
clearing UOTGHS_DEVEPTIMRx.FIFOCON.
SW
write data to CPU
BANK 0
SW
IN
SW
write data to CPU
BANK 1
(bank 0)
DATA
SW
Figure 39-18 on page
HW
ACK
SW
write data to CPU
IN
BANK0
(bank 1)
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
DATA
1089.
ACK