SAM3A4C Atmel Corporation, SAM3A4C Datasheet - Page 726
SAM3A4C
Manufacturer Part Number
SAM3A4C
Description
Manufacturer
Atmel Corporation
- Current page: 726 of 1465
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726
726
SAM3X/A
SAM3X/A
Figure 33-19. TWI Read Operation with Single Data Byte and Internal Address
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
- Internal address size (IADRSZ)
Read Receive Holding register
Set the Master Mode register:
TWI_CR = MSEN + SVDIS
TWI_CR = START | STOP
Read ==> bit MREAD = 1
Set the internal address
Set the Control register:
- Device slave address
TWI_IADR = address
- Transfer direction bit
Read Status register
Read Status register
(Needed only once)
Start the transfer
- Master enable
Yes
TXCOMP = 1?
Set TWI clock
RXRDY = 1?
Yes
BEGIN
END
No
No
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
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