SAM3A4C Atmel Corporation, SAM3A4C Datasheet - Page 81

• Manufacturer Part Number: SAM3A4C
• Manufacturer: Atmel Corporation

11.6.7.2
11.6.7.3
11.6.7.4
11.6.7.5
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Return
Tail-chaining
Late-arriving
Exception entry
When one exception preempts another, the exceptions are called nested exceptions. See
“Exception entry” on page 81
This occurs when the exception handler is completed, and:
The processor pops the stack and restores the processor state to the state it had before the
interrupt occurred. See
This mechanism speeds up exception servicing. On completion of an exception handler, if there
is a pending exception that meets the requirements for exception entry, the stack pop is skipped
and control transfers to the new exception handler.
This mechanism speeds up preemption. If a higher priority exception occurs during state saving
for a previous exception, the processor switches to handle the higher priority exception and initi-
ates the vector fetch for that exception. State saving is not affected by late arrival because the
state saved is the same for both exceptions. Therefore the state saving continues uninterrupted.
The processor can accept a late arriving exception until the first instruction of the exception han-
dler of the original exception enters the execute stage of the processor. On return from the
exception handler of the late-arriving exception, the normal tail-chaining rules apply.
Exception entry occurs when there is a pending exception with sufficient priority and either:
When one exception preempts another, the exceptions are nested.
Sufficient priority means the exception has more priority than any limits set by the mask regis-
ters, see
pending but is not handled by the processor.
When the processor takes an exception, unless the exception is a tail-chained or a late-arriving
exception, the processor pushes information onto the current stack. This operation is referred as
stacking and the structure of eight data words is referred as stack frame. The stack frame con-
tains the following information:
Immediately after stacking, the stack pointer indicates the lowest address in the stack frame.
Unless stack alignment is disabled, the stack frame is aligned to a double-word address. If the
STKALIGN bit of the Configuration Control Register (CCR) is set to 1, stack align adjustment is
performed during stacking.
• there is no pending exception with sufficient priority to be serviced
• the completed exception handler was not handling a late-arriving exception.
• the processor is in Thread mode
• the new exception is of higher priority than the exception being handled, in which case the
• R0-R3, R12
• Return address
• PSR
• LR.
new exception preempts the original exception.
“Exception mask registers” on page
“Exception return” on page 82
more information.
62. An exception with less priority than this is
for more information.
SAM3X/A
SAM3X/A
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