SAM3A4C Atmel Corporation, SAM3A4C Datasheet - Page 1102

• Manufacturer Part Number: SAM3A4C
• Manufacturer: Atmel Corporation

39.5.5
1102
1102
USB DMA Channel X Registers
(Current Transfer Descriptor)
Next Descriptor Address
Memory Area
Data Buffer 1
Data Buffer 2
Data Buffer 3
AHB Address
SAM3X/A
SAM3X/A
USB DMA Channel Transfer Descriptor
Control
Status
(UOTGHS_HSTPIPCFGx.PSIZE / UOTGHS_DEVEPTCFGx.EPSIZE) and the Buffer Byte
L e n g t h
UOTGHS_DEVDMACONTROLx.BUFF_LENGTH) field.
The UOTGHS average throughput may be up to nearly 480 Mbps. Its average access latency
decreases as burst length increases due to the zero wait-state side effect of unchanged
pipe/endpoint. Word access allows reducing the AHB bandwidth required for the USB by four, as
compared to native byte access. If at least 0 wait-state word burst capability is also provided by
the other DMA AHB bus slaves, each of both DMA AHB busses need less than 60% bandwidth
allocation for full USB bandwidth usage at 33 MHz, and less than 30% at 66 MHz.
Figure 39-29. Example of DMA Chained List
The DMA channel transfer descriptor is loaded from the memory. Be careful with the alignment
of this buffer. The structure of the DMA channel transfer descriptor is defined by three parame-
ters as described below:
Offset 0:
Offset 4:
• The address must be aligned: 0xXXXX0
• Next Descriptor Address Register: UOTGHS_xxxDMANXTDSCx
• The address must be aligned: 0xXXXX4
• DMA Channelx Address Register: UOTGHS_xxxDMAADDRESSx
Next Descriptor Address
Transfer Descriptor
AHB Address
Control
( U O T G H S _ H S T D M A C O N T R O L x . B U F F _ L E N G T H
Next Descriptor Address
Transfer Descriptor
AHB Address
Control
Next Descriptor Address
Transfer Descriptor
AHB Address
Control
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
NULL
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