SAM3A4C Atmel Corporation, SAM3A4C Datasheet - Page 989

• Manufacturer Part Number: SAM3A4C
• Manufacturer: Atmel Corporation

38.6.2.2
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Comparator
The comparator continuously compares its counter value with the channel period defined by
CPRD in the
defined by CDTY in the
generate an output signal OCx accordingly.
The different properties of the waveform of the output OCx are:
• A dead-time generator providing two complementary outputs (DTOHx/DTOLx) which allows
• An output override block that can force the two complementary outputs to a programmed
• An asynchronous fault protection mechanism that has the highest priority to override the two
• the clock selection. The channel counter is clocked by one of the clocks provided by the
• the waveform period. This channel parameter is defined in the CPRD field of the
• the waveform duty-cycle. This channel parameter is defined in the CDTY field of the
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to drive external power control switches safely.
value (OOOHx/OOOLx).
complementary outputs in case of fault detection (PWMHx/PWMLx).
clock generator described in the previous section. This channel parameter is defined in the
CPRE field of the
reset at 0.
PWM_CPRDx register.
If the waveform is left aligned, then the output waveform period depends on the counter
source clock and can be calculated:
By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1,
2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be:
By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the
formula becomes, respectively:
If the waveform is center aligned then the output waveform period depends on the counter
source clock and can be calculated:
By using the PWM master clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will
be:
By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the
formula becomes, respectively:
PWM_CDTYx register.
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2
2
X
CRPD
MCK
X
CPRD
CPRD
MCK
MCK
MCK
CPRD
DIVA
“PWM Channel Period Register” on page 1060
DIVA
or
“PWM Channel Mode Register” on page 1056
or
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CRPD
“PWM Channel Duty Cycle Register” on page 1058
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2
MCK
CPRD
DIVB
MCK
DIVB
(PWM_CPRDx) and the duty-cycle
(PWM_CMRx). This field is
(PWM_CDTYx) to
SAM3X/A
SAM3X/A
989
989