SAM3A4C Atmel Corporation, SAM3A4C Datasheet - Page 649

• Manufacturer Part Number: SAM3A4C
• Manufacturer: Atmel Corporation

Figure 31-8. Input Change Interrupt Timings if there are no Additional Interrupt Modes
31.5.11
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Read PIO_ISR
Pin Level
PIO_ISR
MCK
I/O Lines Lock
The other lines are configured in Falling Edge or Low Level detection by default, if they have not
been previously configured. Otherwise, lines 1, 3 and 6 must be configured in Falling Edge/Low
Level detection by writing 32’h0000_004A in PIO_FELLSR.
When an I/O line is controlled by a peripheral (particularly the Pulse Width Modulation Controller
PWM), it can become locked by the action of this peripheral via an input of the PIO controller.
When an I/O line is locked, the write of the corresponding bit in the registers PIO_PER,
PIO_PDR, PIO_MDER, PIO_MDDR, PIO_PUDR, PIO_PUER and PIO_ABSR is discarded in
order to lock its configuration. The user can know at anytime which I/O line is locked by reading
the PIO Lock Status register PIO_LOCKSR. Once an I/O line is locked, the only way to unlock it
is to apply an hardware reset to the PIO Controller.
APB Access
APB Access
SAM3X/A
SAM3X/A
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