SAM3A4C Atmel Corporation, SAM3A4C Datasheet - Page 443

• Manufacturer Part Number: SAM3A4C
• Manufacturer: Atmel Corporation

26.10.3.3
26.10.4
26.10.4.1
26.10.4.2
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Write Mode
Write Cycle
Write is Controlled by NWE (WRITE_MODE = 1)
Write is Controlled by NCS (WRITE_MODE = 0)
The write cycle time is defined as the total duration of the write cycle, that is, from the time where
address is set on the address bus to the point where address may change. The total write cycle
time is equal to:
NWE_CYCLE = NWE_SETUP + NWE_PULSE + NWE_HOLD
= NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD
All NWE and NCS (write) timings are defined separately for each chip select as an integer num-
ber of Master Clock cycles. To ensure that the NWE and NCS timings are coherent, the user
must define the total write cycle instead of the hold timing. This implicitly defines the NWE hold
time and NCS (write) hold times as:
NWE_HOLD = NWE_CYCLE - NWE_SETUP - NWE_PULSE
NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE
The WRITE_MODE parameter in the SMC_MODE register of the corresponding chip select indi-
cates which signal controls the write operation.
Figure 26-11
put on the bus during the pulse and hold steps of the NWE signal. The internal data buffers are
turned out after the NWE_SETUP time, and until the end of the write cycle, regardless of the
programmed waveform on NCS.
Figure 26-11. WRITE_MODE = 1. The write operation is controlled by NWE
Figure 26-12
put on the bus during the pulse and hold steps of the NCS signal. The internal data buffers are
turned out after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of
the programmed waveform on NWE.
NWR0, NWR1
NBS0, NBS1,
A0, A1
D[15:0]
A [23:2]
NWE,
MCK
NCS
shows the waveforms of a write operation with WRITE_MODE set to 1. The data is
shows the waveforms of a write operation with WRITE_MODE set to 0. The data is
SAM3X/A
SAM3X/A
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