SAM3A4C Atmel Corporation, SAM3A4C Datasheet - Page 697

• Manufacturer Part Number: SAM3A4C
• Manufacturer: Atmel Corporation

32.8.2
Name:
Address:
Access:
This register can only be written if the WPEN bit is cleared in
• MSTR: Master/Slave Mode
0 = SPI is in Slave mode.
1 = SPI is in Master mode.
• PS: Peripheral Select
0 = Fixed Peripheral Select.
1 = Variable Peripheral Select.
• PCSDEC: Chip Select Decode
0 = The chip selects are directly connected to a peripheral device.
1 = The four chip select lines are connected to a 4- to 16-bit decoder.
When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit
decoder. The Chip Select Registers define the characteristics of the 15 chip selects according to the following rules:
• MODFDIS: Mode Fault Detection
0 = Mode fault detection is enabled.
1 = Mode fault detection is disabled.
• WDRBT: Wait Data Read Before Transfer
0 = No Effect. In master mode, a transfer can be initiated whatever the state of the Receive Data Register is.
1 = In Master Mode, a transfer can start only if the Receive Data Register is empty, i.e. does not contain any unread data.
This mode prevents overrun error in reception.
• LLB: Local Loopback Enable
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
LLB
SPI_CSR0 defines peripheral chip select signals 0 to 3.
SPI_CSR1 defines peripheral chip select signals 4 to 7.
SPI_CSR2 defines peripheral chip select signals 8 to 11.
SPI_CSR3 defines peripheral chip select signals 12 to 14.
31
23
15
–
–
7
SPI Mode Register
30
22
14
SPI_MR
0x40008004 (0), 0x4000C004 (1)
Read-write
–
–
6
–
WDRBT
29
21
13
–
–
5
MODFDIS
28
20
12
–
–
4
DLYBCS
”SPI Write Protection Mode
27
19
11
–
3
–
PCSDEC
26
18
10
–
2
Register”.
PCS
PS
25
17
–
9
1
SAM3X/A
SAM3X/A
MSTR
24
16
–
8
0
697
697