SAM3A4C Atmel Corporation, SAM3A4C Datasheet - Page 687

• Manufacturer Part Number: SAM3A4C
• Manufacturer: Atmel Corporation

Figure 32-8. Programmable Delays
32.7.3.5
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Chip Select 1
Chip Select 2
Peripheral Selection
SPCK
These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus
release time.
The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By
default, all the NPCS signals are high before and after each transfer.
Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register). In
this case, the current peripheral is defined by the PCS field in SPI_MR and the PCS field in the
SPI_TDR has no effect.
Variable Peripheral Select is activated by setting PS bit to one. The PCS field in SPI_TDR is
used to select the current peripheral. This means that the peripheral selection can be defined for
each new data. The value to write in the SPI_TDR register as the following format.
[xxxxxxx(7-bit) + LASTXFER(1-bit)
equals to the chip select to assert as defined in
LASTXFER bit at 0 or 1 depending on CSAAT bit.
Note:
CSAAT, LASTXFER and CSNAAT bits are discussed in
tion with DMAC”
If LASTXFER is used, the command must be issued before writing the last character. Instead of
LASTXFER, the user can use the SPIDIS command. After the end of the DMA transfer, wait for
the TXEMPTY flag, then write SPIDIS into the SPI_CR register (this will not change the configu-
ration register values); the NPCS will be deactivated after the last character transfer. Then,
another DMA transfer can be started if the SPIEN was previously written in the SPI_CR register.
• The delay before SPCK, independently programmable for each chip select by writing the field
• The delay between consecutive transfers, independently programmable for each chip select
• Fixed Peripheral Select: SPI exchanges data with only one peripheral
• Variable Peripheral Select: Data can be exchanged with more than one peripheral without
DLYBS. Allows the start of SPCK to be delayed after the chip select has been asserted.
by writing the DLYBCT field. Allows insertion of a delay between two transfers occurring on
the same chip select
having to reprogram the NPCS field in the SPI_MR register.
1. Optional.
DLYBCS
.
DLYBS
(1)
+ xxxx(4-bit) + PCS (4-bit) + DATA (8 to 16-bit)] with PCS
Section 32.8.4
DLYBCT
Section 32.7.3.9 ”Peripheral Deselec-
(SPI Transmit Data Register) and
DLYBCT
SAM3X/A
SAM3X/A
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687