SAM3A4C Atmel Corporation, SAM3A4C Datasheet - Page 354

• Manufacturer Part Number: SAM3A4C
• Manufacturer: Atmel Corporation

23.4.4.1
Figure 23-4. Multi Buffer Transfer Using Linked List
354
354
Buffer Chaining Using Linked Lists
DSCRx(0)
SAM3X/A
SAM3X/A
Multi-buffer Transfers
DSCRx(1)
CTRLBx
CTRLAx
DADDRx
SADDRx
In this case, the DMAC re-programs the channel registers prior to the start of each buffer by
fetching the buffer descriptor for that buffer from system memory. This is known as an LLI
update.
DMAC buffer chaining is supported by using a Descriptor Pointer register (DMAC_DSCRx) that
stores the address in memory of the next buffer descriptor. Each buffer descriptor contains the
corresponding buffer descriptor (DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx,
DMAC_CTRLAx DMAC_CTRLBx).
To set up buffer chaining, a sequence of linked lists must be programmed in memory.
The DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLAx and DMAC_CTRLBx
registers are fetched from system memory on an LLI update. The updated content of the
DMAC_CTRLAx register is written back to memory on buffer completion.
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chaining.
The Linked List multi-buffer transfer is initiated by programming DMAC_DSCRx with DSCRx(0)
(LLI(0) base address) different from zero. Other fields and registers are ignored and overwritten
when the descriptor is retrieved from memory.
The last transfer descriptor must be written to memory with its next descriptor address set to 0.
shows how to use chained linked lists in memory to define multi-buffer transfers using buffer
= DSCRx(0) + 0xC
= DSCRx(0) + 0x8
= DSCRx(0) + 0x4
LLI(0)
= DSCRx(0) + 0x0
= DSCRx(0) + 0x10
System Memory
DSCRx(1)
DSCRx(2)
CTRLBx
CTRLBx
DADDRx
SADDRx
LLI(1)
= DSCRx(1) + 0xC
= DSCRx(1) + 0x8
= DSCRx(1) + 0x4
= DSCRx(1) + 0x0
= DSCRx(1) + 0x10
DSCRx(2)
(points to 0 if
LLI(1) is the last
transfer descriptor
Figure 23-4 on page
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12