adsp-21478 Analog Devices, Inc., adsp-21478 Datasheet - Page 10

• Manufacturer Part Number: adsp-21478
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21478/ADSP-21479
or I
maximum of up to 32 I
tle-endian or big-endian transmission formats and word lengths
selectable from 3 bits to 32 bits. For the left-justified and I
modes, data-word lengths are selectable between 8 bits and 32
bits. Serial ports offer selectable synchronization and transmit
modes as well as optional μ-law or A-law companding selection
on a per channel basis. Serial port clocks and frame syncs can be
internally or externally generated.
The serial ports also contain frame sync error detection logic
where the serial ports detect frame syncs that arrive early (for
example frame syncs that arrive while the transmission/recep-
tion of the previous word is occurring). All the serial ports also
share one dedicated error interrupt.
S/PDIF-Compatible Digital Audio Receiver/Transmitter
The S/PDIF receiver/transmitter has no separate DMA chan-
nels. It receives audio data in serial format and converts it into a
biphase encoded signal. The serial data input to the
receiver/transmitter can be formatted as left justified, I
right-justified with word widths of 16, 18, 20, or 24 bits.
The serial data, clock, and frame sync inputs to the S/PDIF
receiver/transmitter are routed through the signal routing unit
(SRU). They can come from a variety of sources such as the
SPORTs, external pins, the precision clock generators (PCGs),
and are controlled by the SRU control registers.
Asynchronous Sample Rate Converter
The sample rate converter (ASRC) contains four ASRC blocks
and is the same core as that used in the AD1896 192 kHz stereo
asynchronous sample rate converter and provides up to 128 dB
SNR. The ASRC block is used to perform synchronous or asyn-
chronous sample rate conversion across independent stereo
channels, without using internal processor resources. The four
SRC blocks can also be configured to operate together to
convert multichannel audio data without phase mismatches.
Finally, the ASRC can be used to clean up audio data from jit-
tery clock sources such as the S/PDIF receiver.
Input Data Port
The IDP provides up to eight serial input channels—each with
its own clock, frame sync, and data inputs. The eight channels
are automatically multiplexed into a single 32-bit by eight-deep
FIFO. Data is always formatted as a 64-bit frame and divided
into two 32-bit words. The serial protocol is designed to receive
audio channels in I
mode. One frame sync cycle indicates one 64-bit left/right pair,
but data is sent to the FIFO as 32-bit words (that is, one-half of a
frame at a time). The processor supports 24- and 32-bit I
and 32-bit left-justified, and 24-, 20-, 18- and 16-bit right-justi-
fied formats.
Precision Clock Generators
The precision clock generators (PCG) consist of four units, each
of which generates a pair of signals (clock and frame sync)
derived from a clock input signal. The units, A B, C, and D, are
2
S channels (using two stereo devices) per serial port, with a
2
S, left-justified sample pair, or right-justified
2
S channels. The serial ports permit lit-
Rev. PrB | Page 10 of 70 | March 2010
2
S or
2
S, 24-
2
S
identical in functionality and operate independently of each
other. The two signals generated by each unit are normally used
as a serial bit clock/frame sync pair.
The outputs of PCG A and B can be routed through the DAI
pins and the outputs of PCG C and D can be driven on to the
DAI as well as the DPI pins.
Digital Peripheral Interface (DPI)
The digital peripheral interface provides connections to two
serial peripheral interface ports (SPI), one universal asynchro-
nous receiver-transmitter (UART), 12 flags, a 2-wire interface
(TWI), three PWM modules (PWM3–1), and two general-pur-
pose timers.
Serial Peripheral (Compatible) Interface
The ADSP-2147x SHARC processors contain two serial periph-
eral interface ports (SPIs). The SPI is an industry-standard
synchronous serial link, enabling the SPI-compatible port to
communicate with other SPI compatible devices. The SPI con-
sists of two data pins, one device select pin, and one clock pin. It
is a full-duplex synchronous serial interface, supporting both
master and slave modes. The SPI port can operate in a multi-
master environment by interfacing with up to four other SPI-
compatible devices, either acting as a master or slave device. The
SPI-compatible peripheral implementation also features pro-
grammable baud rate and clock phase and polarities. The SPI-
compatible port uses open drain drivers to support a multimas-
ter configuration and to avoid data contention.
UART Port
The processors provide a full-duplex Universal Asynchronous
Receiver/Transmitter (UART) port, which is fully compatible
with PC-standard UARTs. The UART port provides a simpli-
fied UART interface to other peripherals or hosts, supporting
full-duplex, DMA-supported, asynchronous transfers of serial
data. The UART also has multiprocessor communication capa-
bility using 9-bit address detection. This allows it to be used in
multidrop networks through the RS-485 data interface
standard. The UART port also includes support for 5 to 8 data
bits, 1 or 2 stop bits, and none, even, or odd parity. The UART
port supports two modes of operation:
The UART port's baud rate, serial data format, error code gen-
eration and status, and interrupts are programmable:
• PIO (programmed I/O) – The processor sends or receives
• DMA (direct memory access) – The DMA controller trans-
• Support for bit rates ranging from (f
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.
fers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
(f
Preliminary Technical Data
PCLK
/16) bits per second.
PCLK
/1,048,576) to