adsp-21478 Analog Devices, Inc., adsp-21478 Datasheet - Page 48

• Manufacturer Part Number: adsp-21478
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21478/ADSP-21479
S/PDIF Receiver
The following section describes timing as it relates to the
S/PDIF receiver.
Internal Digital PLL Mode
In the internal digital phase-locked loop mode the internal PLL
(digital PLL) generates the TBD × FS clock.
Table 41. S/PDIF Receiver Internal Digital PLL Mode Timing
1
Parameter
Switching Characteristics
t
t
t
t
t
Serial clock frequency is TBD x frame sync where FS = the frequency of LRCLK.
DFSI
HOFSI
DDTI
HDTI
SCLKIW
1
(DATA CHANNEL
(SERIAL CLOCK)
(FRAME SYNC)
LRCLK Delay After Serial Clock
LRCLK Hold After Serial Clock
Transmit Data Delay After Serial Clock
Transmit Data Hold After Serial Clock
Transmit Serial Clock Width
DAI_P20–1
DAI_P20–1
DAI_P20–1
A/B)
Figure 35. S/PDIF Receiver Internal Digital PLL Mode Timing
DRIVE EDGE
Rev. PrB | Page 48 of 70 | March 2010
t
HOFSI
t
HDTI
t
t
DFSI
DDTI
t
SCLKIW
Preliminary Technical Data
SAMPLE EDGE
Min
–2
–2
38.5
Max
5
5
Unit
ns
ns
ns
ns
ns