adsp-21478 Analog Devices, Inc., adsp-21478 Datasheet - Page 24

• Manufacturer Part Number: adsp-21478
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21478/ADSP-21479
Clock Input
Table 15. Clock Input
1
2
3
4
5
6
Clock Signals
The ADSP-2147x can use an external clock or a crystal. See the
CLKIN pin description in
processor to use its internal clock generator by connecting the
necessary components to CLKIN and XTAL.
component connections used for a crystal operating in funda-
Parameter
Timing Requirements
t
t
t
t
t
f
t
Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.
Applies only for CLKCFG1–0 = 01 and default values for PLL control bits in PMCTL.
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t
See
Actual input jitter should be combined with ac specifications for accurate timing analysis.
Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.
CK
CKL
CKH
CKRF
CCLK
VCO
CKJ
5, 6
4
Figure 5 on page 22
3
CLKIN
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V to 2.0 V)
CCLK Period
VCO Frequency
CLKIN Jitter Tolerance
for VCO diagram.
Table
t
CKH
9. Programs can configure the
C1
22pF
CLKIN
*TYPICAL VALUES
Figure 8
Figure 8. 266 MHz Operation (Fundamental Mode Crystal)
t
CK
25 MHz
t
R1
1M *
CKL
Y1
Rev. PrB | Page 24 of 70 | March 2010
Figure 7. Clock Input
ADSP-2147x
shows the
XTAL
R2
47 *
C2
22pF
Min
TBD
TBD
TBD
10
TBD
–250
1
mental mode. Note that the clock rate is achieved using a 16.67
MHz crystal and a PLL multiplier ratio 16:1 (CCLK:CLKIN
achieves a clock speed of 266 MHz). To achieve the full core
clock rate, programs need to configure the multiplier bits in the
PMCTL register.
R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL
DRIVE POWER. REFER TO CRYSTAL
MANUFACTURER’S SPECIFICATIONS
100 MHz
Preliminary Technical Data
CCLK
Max
TBD
TBD
TBD
TBD
TBD
200
+250
.
2
t
CKJ
Min
11.25
11.25
3.75
–250
22.5
200
1
266 MHz
Max
100
45
45
6
10
533
+250
2
Unit
ns
ns
ns
ns
ns
MHz
ps