adsp-21478 Analog Devices, Inc., adsp-21478 Datasheet - Page 47

• Manufacturer Part Number: adsp-21478
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
S/PDIF Transmitter Input Data Timing
The timing requirements for the S/PDIF transmitter are given
in
using the SRU. Therefore, the timing specifications provided
below are valid at the DAI_P20–1 pins.
Table 39. S/PDIF Transmitter Input Data Timing
1
Oversampling Clock (HFCLK) Switching Characteristics
The S/PDIF transmitter has an oversampling clock. This
HFCLK input is divided down to generate the biphase clock.
Table 40. Over Sampling Clock (HFCLK) Switching Characteristics
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
Parameter
HFCLK Frequency for HFCLK = 384 × Frame Sync
HFCLK Frequency for HFCLK = 256 × Frame Sync
Frame Rate (FS)
The serial clock, data and frame sync signals can come from any of the DAI pins.The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can
SISFS
SIHFS
SISD
SIHD
SIHFCLKW
SIHFCLK
SISCLKW
SISCLK
be either CLKIN or any of the DAI pins.
Table
1
1
1
1
39. Input signals are routed to the DAI_P20–1 pins
Frame Sync Setup Before Serial Clock Rising Edge
Frame Sync Hold After Serial Clock Rising Edge
Data Setup Before Serial Clock Rising Edge
Data Hold After Serial Clock Rising Edge
Transmit Clock Width
Transmit Clock Period
Clock Width
Clock Period
(SERIAL CLOCK)
(FRAME SYNC)
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
(TxCLK)
(DATA)
t
SITXCLKW
Figure 34. S/PDIF Transmitter Input Timing
Rev. PrB | Page 47 of 70 | March 2010
SAMPLE EDGE
t
SISCLKW
t
SISFS
t
SISD
t
SISCLK
t
SITXCLK
Max
Oversampling Ratio × Frame Sync <= 1/t
192.0
49.2
ADSP-21478/ADSP-21479
Min
3
3
3
3
9
20
36
80
t
t
SIHFS
SIHD
Max
SIHFCLK
Unit
MHz
MHz
kHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns