adsp-21478 Analog Devices, Inc., adsp-21478 Datasheet - Page 32

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adsp-21478

Manufacturer Part Number
adsp-21478
Description
Sharc Processor
Manufacturer
Analog Devices, Inc.
Datasheet

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ADSP-21478/ADSP-21479
SDRAM Interface Enable/Disable Timing (133 MHz SDCLK)
Table 27. SDRAM Interface Enable/Disable Timing
1
Parameter
Switching Characteristics
t
t
t
t
t
t
For f
DSDC
ENSDC
DSDCC
ENSDCC
DSDCA
ENSDCA
CCLK
= 266 MHz (core clock to SDCLK ratio = 1:2).
Command Disable After CLKIN Rise
Command Enable After CLKIN Rise
SDCLK Disable After CLKIN Rise
SDCLK Enable After CLKIN Rise
Address Disable After CLKIN Rise
Address Enable After CLKIN Rise
COMMAND
COMMAND
SDCLK
SDCLK
CLKIN
ADDR
ADDR
Figure 20. SDRAM Interface Enable/Disable Timing
Rev. PrB | Page 32 of 70 | March 2010
1
t
t
t
t
t
ENSDCA
ENSDCC
t
DSDCC
DSDCA
ENSDC
DSDC
Preliminary Technical Data
4.0
3.8
Min
2 × t
PCLK
– 4
Max
2 × t
8.5
9.2
4 × t
PCLK
PCLK
+ 3
Unit
ns
ns
ns
ns
ns
ns

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