adsp-21478 Analog Devices, Inc., adsp-21478 Datasheet - Page 15

• Manufacturer Part Number: adsp-21478
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Table 9. Pin Descriptions (Continued)
Name
SDRAS
SDCAS
SDWE
SDCKE
SDA10
SDDQM
SDCLK
DAI _P
DPI _P
WDT_CLKIN
WDT_CLKO
WDTRSTO
THD_P
THD_M
The following symbols appear in the Type column of
O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic
levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors
cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26k–63kΩ.
The range of an ipd resistor can be between 31k–85kΩ.
In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins.
Not all pins are available in the 100-lead LQFP package. For more information, see
14–1
20–1
Type
O/T (ipu)
O/T (ipu)
O/T (ipu)
O/T (ipu)
O/T (ipu)
O/T (ipu)
O/T (ipd)
I/O/T (ipu)
I/O/T (ipu)
I
O
O (ipu)
I
O
State During/
After Reset
High-Z/
driven high
High-Z/
driven high
High-Z/
driven high
High-Z/
driven high
High-Z/
driven high
High-Z/
driven high
High-Z/
driving
High-Z
High-Z
Rev. PrB | Page 15 of 70 | March 2010
Table
Description
SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with
other SDRAM command pins, defines the operation for the SDRAM to perform.
SDRAM Column Address Select. Connect to SDRAM’s CAS pin. In conjunction
with other SDRAM command pins, defines the operation for the SDRAM to
perform.
SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin.
SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK
signal. For details, see the data sheet supplied with the SDRAM device.
SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with non-
SDRAM accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses.
DQM Data Mask. SDRAM Input mask signal for write accesses and
ADSP-2147x output enable signal for read accesses. Input data is masked when
DQM is sampled high during a write cycle. The output buffers are placed in a High-
Z state when DQM is sampled high during a read cycle.
SDRAM Clock Output. Clock driver for this pin differs from all other clock drivers.
See
Digital Applications Interface. These pins provide the physical interface to the
DAI SRU. The DAI SRU configuration registers define the combination of on-chip
audiocentric peripheral inputs or outputs connected to the pin and to the pin’s
output enable. The configuration registers of these peripherals then determines
the exact behavior of the pin. Any input or output signal present in the DAI SRU
may be routed to any of these pins. The DAI SRU provides the connection from
the serial ports, the S/PDIF module, input data ports (2), and the precision clock
generators (4), to the DAI_P20–1 pins.
Digital Peripheral Interface. These pins provide the physical interface to the DPI
SRU. The DPI SRU configuration registers define the combination of on-chip
peripheral inputs or outputs connected to the pin and to the pin's output enable.
The configuration registers of these peripherals then determines the exact
behavior of the pin. Any input or output signal present in the DPI SRU may be
routed to any of these pins. The DPI SRU provides the connection from the timers
(2), SPIs (2), UART (1), flags (12), and general-purpose I/O (9) to the DPI_P14–1 pins.
Watch Dog Timer Clock Input. This pin should be pulled low when not used.
Watch Dog Resonator Pad Output.
Watch Dog Timer Reset Out.
Thermal Diode Anode. When not used, this pin can be left floating.
Thermal Diode Cathode. When not used, this pin can be left floating.
9: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,
Figure 49 on page
61.
Table 2 on Page 3
ADSP-21478/ADSP-21479
and
Table 53 on Page
64.