adsp-21478 Analog Devices, Inc., adsp-21478 Datasheet - Page 6

• Manufacturer Part Number: adsp-21478
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21478/ADSP-21479
floating-point storage format is supported that effectively dou-
bles the amount of data that may be stored on-chip. Conversion
between the 32-bit floating-point and 16-bit floating-point
formats is performed in a single instruction. While each mem-
ory block can store combinations of code and data, accesses are
most efficient when one block stores data using the DM bus for
transfers, and the other block stores instructions and data using
the PM bus for transfers.
Using the DM bus and PM buses, with one bus dedicated to a
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache.
Table 3. Internal Memory Space (ADSP-21478)
1
Long Word (64 Bits)
Block 0 ROM (Reserved)
0x0004 0000–0x0004 7FFF
Reserved
0x0004 8000–0x0004 8FFF
Block 0 SRAM
0x0004 9000–0x0004 CFFF
Reserved
0x0004 D000–0x0004 FFFF
Block 1 ROM (Reserved)
0x0005 0000–0x0005 7FFF
Reserved
0x0005 8000–0x0005 8FFF
Block 1 SRAM
0x0005 9000–0x0005 CFFF
Reserved
0x0005 D000–0x0005 FFFF
Block 2 SRAM
0x0006 0000–0x0006 1FFF
Reserved
0x0006 2000– 0x0006 FFFF
Block 3 SRAM
0x0007 0000–0x0007 1FFF
Reserved
0x0007 2000–0x0007 FFFF
Some ADSP-2147x processors include a customer-definable ROM block. ROM addresses on these models are not reserved as shown in this table. Please contact your Analog
Devices sales representative for additional details.
Extended Precision Normal or
Instruction Word (48 Bits)
Block 0 ROM (Reserved)
0x0008 0000–0x0008 AAA9
Reserved
0x0008 AAAA–0x0008 BFFF
Block 0 SRAM
0x0008 C000–0x0009 1554
Reserved
0x0009 1555–0x0009 5554
Block 1 ROM (Reserved)
0x000A 0000–0x000A AAA9
Reserved
0x000A AAAA–0x000A BFFF
Block 1 SRAM
0x000A C000–0x000B 1554
Reserved
Block 2 SRAM
0x000C 0000–0x000C 2AA9
Reserved
0x000C 2AAA–0x0000 D5554
Block 3 SRAM
0x000E 0000–0x000E 2AA9
Reserved
0x000E 2AAA–0x000F 0000
0x000B 1555–0x000B 5554
IOP Registers 0x0000 0000–0x0003 FFFF
1
Rev. PrB | Page 6 of 70 | March 2010
Normal Word (32 Bits)
Block 0 ROM (Reserved)
0x0008 0000–0x0008 FFFF
Reserved
0x0009 0000–0x0009 1FFF
Block 0 SRAM
0x0009 2000–0x0009 9FFF
Reserved
0x0009 A000–0x0009 FFFF
Block 1 ROM (Reserved)
0x000A 0000–0x000A FFFF
Reserved
0x000B 0000–0x000B 1FFF
Block 1 SRAM
0x000B 2000–0x000B 9FFF
Reserved
0x000B A000–0x000B FFFF
Block 2 SRAM
0x000C 0000–0x000C 3FFF
Reserved
0x000C 4000–0x000D FFFF
Block 3 SRAM
0x000E 0000–0x000E 3FFF
Reserved
0x000E 4000–0x000F FFFF
The memory maps in
memory address space of the processors. The 48-bit space sec-
tion describes what this address range looks like to an
instruction that retrieves 48-bit memory. The 32-bit section
describes what this address range looks like to an instruction
that retrieves 32-bit memory.
On-Chip Memory Bandwidth
The internal memory architecture allows programs to have four
accesses at the same time to any of the four blocks (assuming
there are no block conflicts). The total bandwidth is realized
using the DMD and PMD buses (2 x 64-bits, CCLK speed) and
the IOD0/1 buses (2 x 32-bit, PCLK speed).
Preliminary Technical Data
Table 4
and
Short Word (16 Bits)
Block 0 ROM (Reserved)
0x0010 0000–0x0011 FFFF
Reserved
0x0012 0000–0x0012 FFFF
Block 0 SRAM
0x0012 4000–0x0013 3FFF
Reserved
0x0013 4000–0x0013 FFFF
Block 1 ROM (Reserved)
0x0014 0000–0x0015 FFFF
Reserved
0x0016 0000–0x0016 3FFF
Block 1 SRAM
0x0016 4000–0x0017 3FFF
Reserved
0x0017 4000–0x0017 FFFF
Block 2 SRAM
0x0018 0000–0x0018 7FFF
Reserved
0x0018 8000–0x001B FFFF
Block 3 SRAM
0x001C 0000–0x001C 7FFF
Reserved
0x001C 8000–0x001F FFFF
Table 5
display the internal