adsp-21478 Analog Devices, Inc., adsp-21478 Datasheet - Page 8

• Manufacturer Part Number: adsp-21478
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21478/ADSP-21479
External Memory
The external port provides a high performance, glueless inter-
face to a wide variety of industry-standard memory devices. The
external port, available in the 196-ball CSP_BGA package, may
be used to interface to synchronous and/or asynchronous mem-
ory devices through the use of its separate internal memory
controllers. The first is an SDRAM controller for connection of
industry-standard synchronous DRAM devices and DIMMs
(dual inline memory module), while the second is an asynchro-
nous memory controller intended to interface to a variety of
memory devices. Four memory select pins enable up to four
separate devices to coexist, supporting any desired combination
of synchronous and asynchronous device types. Non-SDRAM
external memory address space is shown in
SIMD Access to External Memory
The SDRAM controller on the processor supports SIMD access
on the 64-bit EPD (external port data bus) which allows to
access the complementary registers on the PEy unit in the nor-
mal word space (NW). This improves performance since there
is no need to explicitly load the complimentary registers as in
SISD mode.
Table 5. External Memory for Non-SDRAM Addresses
External Memory Execution
In the ADSP-21479, the program sequencer can execute code
directly from external memory bank 0 (SRAM, SDRAM). This
allows a reduction in internal memory size. With external exe-
cution, programs run at slower speeds since 48-bit instructions
are fetched in parts from a 16-bit external bus coupled with the
inherent latency of fetching instructions from SDRAM. Fetch-
ing instructions from SDRAM generally takes 1.5 peripheral
clock cycles per instruction.
Bank
Bank 0
Bank 1
Bank 2
Bank 3
• An SDRAM controller that supports a glueless interface
• Arbitration logic to coordinate core and DMA transfers
supports 14M words of external memory in bank 0 and
16M words of external memory in bank 1, bank 2, and
bank 3.
with any of the standard SDRAMs. The SDC supports 62M
words of external memory in bank 0, and 64M words of
external memory in bank 1, bank 2, and bank 3.
between internal and external memory over the external
port.
Size in
Words
14M
16M
16M
16M
Address Range
0x0020 0000–0x00FF FFFF
0x0400 0000–0x04FF FFFF
0x0800 0000–0x08FF FFFF
0x0C00 0000–0x0CFF FFFF
Table
5.
Rev. PrB | Page 8 of 70 | March 2010
VISA and Non VISA Access to External Memory
The SDRAM controller on the processor supports VISA code
operation which reduces the memory load since the VISA
instructions are compressed. Moreover, bus fetching is reduced
because in the best case one 48-bit fetch contains 3 valid instruc-
tions. Code execution from the traditional non-VISA operation
is also supported. Note that code execution is only supported
from bank 0 regardless of VISA/non-VISA.
SDRAM Controller
The SDRAM controller, available on the ADSP-21479 in the
196-ball CSP_BGA package, provides an interface of up to four
separate banks of industry-standard SDRAM devices or
DIMMs, at speeds up to f
standard, each bank has its own memory select line
(MS0–MS3), and can be configured to contain between
16M bytes and 128M bytes of memory. SDRAM external mem-
ory address space is shown in
Table 6. External Memory for SDRAM Addresses
A set of programmable timing parameters is available to config-
ure the SDRAM banks to support slower memory devices. Note
that 32-bit wide devices are not supported on SDRAM and the
AMI interface.
The SDRAM controller address, data, clock, and control pins
can drive loads up to distributed 30 pF loads. For larger memory
systems, the SDRAM controller external buffer timing should
be selected and external buffering should be provided so that the
load on the SDRAM controller pins does not exceed 30 pF.
Note that the external memory bank addresses shown are for
normal-word (32-bit) accesses. If 48-bit instructions as well as
32-bit data are both placed in the same external memory bank,
care must be taken while mapping them to avoid overlap. In
case of 16-bit wide external memory, two 48-bit instructions are
stored in six 32-bit wide memory locations. For example, if 2k
instructions are placed in 16-bit wide external memory starting
at the bank 0 normal-word base address 0x0030 0000
(corresponding to instruction address 0x0020 0000) and ending
at address 0x0030 0BFF (corresponding to instruction address
0x0020 07FF), then data buffers can be placed starting at an
address that is offset by 3k 32-bit words (for example, starting at
0x0030 0C00).
Bank
Bank 0
Bank 1
Bank 2
Bank 3
Preliminary Technical Data
Size in
Words
62M
64M
64M
64M
SDCLK
. Fully compliant with the SDRAM
Table
Address Range
0x0020 0000–0x03FF FFFF
0x0400 0000–0x07FF FFFF
0x0800 0000–0x0BFF FFFF
0x0C00 0000–0x0FFF FFFF
6.