adsp-21478 Analog Devices, Inc., adsp-21478 Datasheet - Page 39

• Manufacturer Part Number: adsp-21478
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Table 32. Serial Ports—External Late Frame Sync
1
1
Parameter
Switching Characteristics
t
t
The t
This figure reflects changes made to support left-justified mode.
DDTLFSE
DDTENFS
DDTLFSE
1
1
and t
DDTENFS
Data Delay from Late External Transmit Frame Sync or External Receive
Frame Sync with MCE = 1, MFD = 0
Data Enable for MCE = 1, MFD = 0
(DATA CHANNEL
(DATA CHANNEL
(FRAME SYNC)
(FRAME SYNC)
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
parameters apply to left-justified as well as DSP serial mode, and MCE = 1, MFD = 0.
(SCLK)
(SCLK)
A/B)
A/B)
NOTES
1. SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20–1 PINS
USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20–1 PINS.
THE CHARACTERIZED SPORT AC TIMINGS ARE APPLICABLE WHEN INTERNAL CLOCKS AND
FRAMES ARE LOOPED BACK FROM THE PIN, NOT ROUTED DIRECTLY THROUGH THE SRU.
DRIVE
DRIVE
t
t
DDTLFSE
DDTLFSE
t
t
DDTENFS
DDTENFS
t
t
Figure 24. External Late Frame Sync
Rev. PrB | Page 39 of 70 | March 2010
SFSE/I
SFSE/I
SAMPLE
SAMPLE
t
t
HFSE/I
HFSE/I
1ST BIT
1ST BIT
LATE EXTERNAL TRANSMIT FS
DRIVE
DRIVE
t
t
HDTE/I
HDTE/I
1
ADSP-21478/ADSP-21479
Min
0.5
t
t
DDTE/I
DDTE/I
2ND BIT
2ND BIT
Max
10
Unit
ns
ns