adsp-21478 Analog Devices, Inc., adsp-21478 Datasheet - Page 41

• Manufacturer Part Number: adsp-21478
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Input Data Port (IDP)
The timing requirements for the IDP are given in
signals are routed to the DAI_P20–1 pins using the SRU. There-
fore, the timing specifications provided below are valid at the
DAI_P20–1 pins.
Table 34. Input Data Port (IDP)
1
Parameter
Timing Requirements
t
t
t
t
t
t
The serial clock, data and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG's
SISFS
SIHFS
SISD
SIHD
IDPCLKW
IDPCLK
input can be either CLKIN or any of the DAI pins.
1
1
1
1
Frame Sync Setup Before Serial Clock Rising Edge
Frame Sync Hold After Serial Clock Rising Edge
Data Setup Before Serial Clock Rising Edge
Data Hold After Serial Clock Rising Edge
Clock Width
Clock Period
(SERIAL CLOCK)
(FRAME SYNC)
DAI_P20–1
DAI_P20–1
DAI_P20–1
(DATA)
Table
Rev. PrB | Page 41 of 70 | March 2010
Figure 26. IDP Master Timing
34. IDP
t
IPDCLKW
t
SISFS
SAMPLE EDGE
t
SISD
t
t
SIHFS
SIHD
t
Min
3.8
2.5
2.5
2.5
(t
t
IPDCLK
PCLK
PCLK
ADSP-21478/ADSP-21479
× 4
× 4) ÷ 2 – 1
Max
Unit
ns
ns
ns
ns
ns
ns