adsp-21478 Analog Devices, Inc., adsp-21478 Datasheet - Page 31

• Manufacturer Part Number: adsp-21478
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
SDRAM Interface Timing (133 MHz SDCLK)
The 133 MHz access speed is for a single processor. The proces-
sor needs to be programmed in t
operated at 266 MHz.
Table 26. SDRAM Interface Timing
1
2
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
For f
Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDCKE, and DQM.
SSDAT
HSDAT
SDCLK
SDCLKH
SDCLKL
DCAD
HCAD
DSDAT
ENSDAT
CCLK
= 266 MHz (core clock to SDCLK ratio = 1:2).
DATA Setup Before SDCLK
DATA Hold After SDCLK
SDCLK Period
SDCLK Width High
SDCLK Width Low
Command, ADDR, Data Delay After SDCLK
Command, ADDR, Data Hold After SDCLK
Data Disable After SDCLK
Data Enable After SDCLK
CMND ADDR
DATA (OUT)
DATA (IN)
SDCLK
(OUT)
SDCLK
= 2.0 × t
1
CCLK
t
SSDAT
mode when
Rev. PrB | Page 31 of 70 | March 2010
Figure 19. SDRAM Interface Timing
2
2
t
DCAD
t
SDCLK
t
t
HSDAT
ENSDAT
t
t
DCAD
HCAD
ADSP-21478/ADSP-21479
t
SDR_CLKL
Min
500
1.23
7.5
2.6
2.6
1.2
1.3
t
HCAD
t
SDCLKH
t
DSDAT
Max
4.8
5.3
Unit
ps
ns
ns
ns
ns
ns
ns
ns
ns