adsp-21478 Analog Devices, Inc., adsp-21478 Datasheet - Page 35

• Manufacturer Part Number: adsp-21478
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries. Note that timing for AMI_ACK, ADDR, DATA, AMI_RD,
AMI_WR, and strobe timing parameters only apply to asyn-
chronous access mode.
Table 29. Memory Write—Bus Master
1
2
3
4
5
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
W = (number of wait states specified in AMICTLx register) × t
H = (number of hold cycles specified in AMICTLx register) x t
AMI_ACK delay/setup: System must meet t
The falling edge of AMI_MSx is referenced.
Note that timing for AMI_ACK, ADDR, DATA, AMI_RD, AMI_WR, and strobe timing parameters only applies to asynchronous access mode.
See
For Write to Write: 1 + HC, for both same bank and different bank. For Write to Read: 3 SDCLK cycles + HC , for the same bank and different banks.
DAAK
DSAK
DAWH
DAWL
WW
DDWH
DWHA
DWHD
DATRWH
WWR
DDWR
WDE
Test Conditions on Page 61
AMI_ACK Delay from Address, Selects
AMI_ACK Delay from AMI_WR Low
Address, Selects to AMI_WR Deasserted
Address, Selects to AMI_WR Low
AMI_WR Pulse Width
Data Setup Before AMI_WR High
Address Hold After AMI_WR Deasserted
Data Hold After AMI_WR Deasserted
Data Disable After AMI_WR Deasserted
AMI_WR High to AMI_WR Low
Data Disable Before AMI_RD Low
AMI_WR Low to Data Enabled
for calculation of hold times given capacitive and dc loads.
DAAK
, or t
DSAK
, for deassertion of AMI_ACK (low). For asynchronous assertion of AMI_ACK (high) user must meet t
5
2
Rev. PrB | Page 35 of 70 | March 2010
1, 3
1, 2
4
2
SDCLK
SDCLK
Min
t
t
W – 1.3
t
H + 0.15
H + 0.02
t
t
2 × t
t
SDCLK
SDCLK
SDCLK
SDCLK
SDCLK
SDCLK
SDCLK
– 3.6 + W
– 2.7
– 1.5+ H
– 3.0 + W
– 1.37 + H
– 4.1
– 5.1
ADSP-21478/ADSP-21479
Max
t
W – 7.1
t
SDCLK
SDCLK
– 10.1 + W
+ 4.9+ H
DAAK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
or t
DSAK
.