adsp-21478 Analog Devices, Inc., adsp-21478 Datasheet - Page 5

• Manufacturer Part Number: adsp-21478
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
signal processing, and are commonly used in digital filters and
Fourier transforms. The two DAGs of the processors contain
sufficient registers to allow the creation of up to 32 circular buf-
fers (16 primary register sets, 16 secondary). The DAGs
automatically handle address pointer wraparound, reduce over-
head, increase performance, and simplify implementation.
Circular buffers can start and end at any memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the
ADSP-2147x can conditionally execute a multiply, an add, and a
subtract in both processing elements while branching and fetch-
ing up to four 32-bit values from memory—all in a single
instruction.
Variable Instruction Set Architecture (VISA)
In addition to supporting the standard 48-bit instructions from
previous SHARC processors, the ADSP-2147x supports new
instructions of 16 and 32 bits. This feature, called Variable
Instruction Set Architecture (VISA), drops redundant/unused
bits within the 48-bit instruction to create more efficient and
80-BIT
MRF
SIMD Core
MULTIPLIER
DAG1
16x32
DMD/PMD 64
80-BIT
MRB
SHIFTER
DAG2
16x32
ALU
Figure 2. SHARC Core Block Diagram
Rev. PrB | Page 5 of 70 | March 2010
JTAG
16x40-BIT
ASTATx
STYKx
Rx/Fx
PEx
RF
FLAG
PROGRAM SEQUENCER
TIMER
5 STAGE
DATA
SWAP
INTERRUPT
compact code. The program sequencer supports fetching these
16-bit and 32-bit instructions from both internal and external
SDRAM memory. This support is not extended to the asynchro-
nous memory interface (AMI). Source modules need to be built
using the VISA option, in order to allow code generation tools
to create these more efficient opcodes.
On-Chip Memory
The ADSP-21478 processor contains 3 Mbits of internal RAM
(Table
internal RAM
ferent combinations of code and data storage. Each memory
block supports single-cycle, independent accesses by the core
processor and I/O processor. The ADSP-2147x memory archi-
tecture, in combination with its separate on-chip buses, allow
two data transfers from the core and one from the I/O proces-
sor, in a single cycle.
The processor’s SRAM can be configured as a maximum of
160k words of 32-bit data, 320k words of 16-bit data, 106.7k
words of 48-bit instructions (or 40-bit data), or combinations of
different word sizes up to 5 megabits. All of the memory can be
accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit
16x40-BIT
ASTATy
Sx/SFx
STYKy
PEy
RF
3) and the ADSP-21479 processor contains 5 Mbits of
CACHE
ADSP-21478/ADSP-21479
PM ADDRESS 32
DM ADDRESS 32
PM DATA 64
DM DATA 64
ALU
(Table
PM ADDRESS 24
PM DATA 48
SHIFTER
4). Each block can be configured for dif-
80-BIT
MSB
MULTIPLIER
4x32-BIT
SYSTEM
USTAT
64-BIT
I/F
PX
80-BIT
MSF