adsp-21478 Analog Devices, Inc., adsp-21478 Datasheet - Page 56

• Manufacturer Part Number: adsp-21478
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21478/ADSP-21479
Shift Register
Table 47. Shift Register
1
2
3
4
5
6
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
t
t
t
f
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DAI_P08
Both clocks can be connected to the same clock source. If both clocks are connected to same clock source, then data in the 18-stage shift register is always one cycle ahead of
For setup/hold timing requirements of off-chip shift register interfacing devices.
SPORTx Serial clock out, Frame sync out, and Serial data outputs are routed to Shift register block internally and are also routed onto DAI_P20
PCG Serial clock output is routed to SPORT and Shift register block internally and are also routed onto DAI_P20
PCG Serial clock and Frame sync outputs are routed to SPORT and Shift register block internally and are also routed onto DAI_P20
SSDI
HSDI
SSDIDAI
HSDIDAI
SSCK
SSCK
CLRREM
CLRREM
CLRW
SCKW
LCKW
MAX
DSDO
DSDO
DSDODAI
DSDODAI
DSDOSP
DSDOSP
DSDOPCG
DSDOPCG
DSDOCLR
DSDOCLR
DLDO
DLDO
DLDODAI
DLDODAI
DLDOSP
DLDOSP
DLDOPCG
DLDOPCG
DLDOCLR
DLDOCLR
latch register data.
2
2
1
2
1
2
LCK
LCKDAI
3
3
3
3
1
2
2
1
2
1
2
1
1
2
SCK
LCK
1
2
1
2
1
2
3, 4
3, 4
3, 4
3, 4
1
2
1
2
2
1, 3
1, 3
3
3
3
3
3
3
3, 5, 6
3, 5, 6
3, 5, 6
3, 5, 6
–
1, 2
01 are selected as shift register clock, latch clock and serial data input.
SR_SDI Setup Before SR_SCLK Rising Edge
SR_SDI Hold After SR_SCLK Rising Edge
DAI_P08–01 (SR_SDI) Setup Before DAI_P08–01 (SR_SCLK) Rising Edge
DAI_P08–01 (SR_SDI) Hold After DAI_P08–01 (SR_SCLK) Rising Edge
SR_SCLK to SR_LAT Setup
DAI_P08–01 (SR_SCLK) to DAI_P08–01 (SR_LAT) Setup
Removal Time SR_CLR to SR_SDCLK
Removal Time SR_CLR to SR_LAT
SR_CLR Pulse Width
SR_SDCLK Clock Pulse Width
SR_LAT Clock Pulse Width
Maximum Clock Frequency SR_SDCLK or SR_LAT
SR_SDO Hold After SR_SCLK Rising Edge
SR_SDO Max. Delay After SR_SCLK Rising Edge
SR_SDO Hold After DAI_P08–01 (SR_SCLK) Rising Edge
SR_SDO Max. Delay After DAI_P08–01 (SR_SCLK) Rising Edge
SR_SDO Hold After DAI_P20–01 (SR_SCLK) Rising Edge
SR_SDO Max. Delay After DAI_P20–01 (SR_SCLK) Rising Edge
SR_SDO Hold After DAI_P20–01 (SR_SCLK) Rising Edge
SR_SDO Max. Delay After DAI_P20–01 (SR_SCLK) Rising Edge
SR_CLR to SR_SDO Min. Delay
SR_CLR to SR_SDO Max. Delay
SR_LDO Hold After SR_LAT Rising Edge
SR_LDO Max. Delay After SR_LAT Rising Edge
SR_LDO Hold After DAI_P08–01 (SR_LAT) Rising Edge
SR_LDO Max. Delay After DAI_P08–01 (SR_LAT) Rising Edge
SR_LDO Hold After DAI_P20–01 (SR_LAT) Rising Edge
SR_LDO Max. Delay After DAI_P20–01 (SR_LAT) Rising Edge
SR_LDO Hold After DAI_P20–01 (SR_LAT) Rising Edge
SR_LDO Max. Delay After DAI_P20–01 (SR_LAT) Rising Edge
SR_CLR to SR_LDO Min. Delay
SR_CLR to SR_LDO Max. Delay
Rev. PrB | Page 56 of 70 | March 2010
Preliminary Technical Data
–
01. SPORT will generate SR_LAT and SDI internally.
Min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
–
01. SPORT will generate SDI internally.
Max
TBD
TBD
f
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
CCLK
–
÷ 8
01.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns