adsp-21478 Analog Devices, Inc., adsp-21478 Datasheet - Page 44

• Manufacturer Part Number: adsp-21478
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21478/ADSP-21479
Sample Rate Converter—Serial Output Port
For the serial output port, the frame-sync is an input and it
should meet setup and hold times with regard to the serial clock
on the output port. The serial data output has a hold time and
Table 37. ASRC, Serial Output Port
1
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
The serial clock, data and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input
SRCSFS
SRCHFS
SRCCLKW
SRCCLK
SRCTDD
SRCTDH
can be either CLKIN or any of the DAI pins.
1
1
1
1
Frame Sync Setup Before Serial Clock Rising Edge
Frame Sync Hold After Serial Clock Rising Edge
Clock Width
Clock Period
Transmit Data Delay After Serial Clock Falling Edge
Transmit Data Hold After Serial Clock Falling Edge
(SERIAL CLOCK)
(FRAME SYNC)
DAI_P20–1
DAI_P20–1
DAI_P20–1
(DATA)
t
SRCTDH
Figure 29. ASRC Serial Output Port Timing
Rev. PrB | Page 44 of 70 | March 2010
t
SRCTDD
t
SRCCLKW
t
SRCSFS
SAMPLE EDGE
delay specification with regard to serial clock. Note that serial
clock rising edge is the sampling edge and the falling edge is the
drive edge.
t
SRCHFS
Preliminary Technical Data
t
SRCCLK
Min
TBD
TBD
(t
t
TBD
PCLK
PCLK
× 4
× 4) ÷ 2 – 1
Max
TBD
Unit
ns
ns
ns
ns
ns
ns