adsp-21478 Analog Devices, Inc., adsp-21478 Datasheet - Page 22

• Manufacturer Part Number: adsp-21478
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21478/ADSP-21479
The VCO frequency is calculated as follows:
f
f
where:
f
PLLM = Multiplier value programmed in the PMCTL register.
During reset, the PLLM value is derived from the ratio selected
using the CLK_CFG pins in hardware.
PLLD = 2, 4, 8, or 16 based on the divider value programmed on
the PMCTL register. During reset this value is 2.
f
f
f
VCO
CCLK
VCO
INPUT
INPUT
INPUT
• The product of CLKIN and PLLM must never exceed 1/2 of
• The product of CLKIN and PLLM must never exceed f
f
(INDIV = 0).
(max) in
(INDIV = 1).
= 2 × PLLM × f
= VCO output
XTAL
VCO
= (2 × PLLM × f
= is the input frequency to the PLL.
= CLKIN when the input divider is disabled or
= CLKIN ÷ 2 when the input divider is enabled
(max) in
BUF
CLKIN
Table 15
4096 CLKIN
DELAY OF
CYCLES
Table 15
INPUT
INPUT
if the input divider is enabled
DIVIDER
PMCTL
CLKIN
(INDIV)
) ÷ PLLD
if the input divider is not enabled
f
INPUT
Figure 5. Core Clock and System Clock Relationship to CLKIN
CLK_CFGx/PMCTL (2xPLLM)
FILTER
LOOP
MULTIPLIER
Rev. PrB | Page 22 of 70 | March 2010
CLKOUT (TEST ONLY)
PLL
PLL
VCO
VCO
f
VCO
DIVIDER
PMCTL
(PLLD)
PLL
Note the definitions of the clock periods that are a function of
CLKIN and the appropriate ratio control shown in and
Table
peripherals are defined in relation to t
specific section for each peripheral’s timing information.
Table 13. Clock Periods
Figure 5
lator or crystal. The shaded divider/multiplier blocks denote
where clock ratios can be set through hardware or software
using the power management control register (PMCTL). For
more information, see the ADSP-214xx SHARC Processor Hard-
ware Reference.
Timing
Requirements
t
t
t
t
CK
CCLK
PCLK
SDCLK
Preliminary Technical Data
f
13. All of the timing specifications for the ADSP-2147x
CCLK
shows core to CLKIN relationships with external oscil-
(PLLBP)
PMCTL
CCLK
Description
CLKIN Clock Period
Processor Core Clock Period
Peripheral Clock Period = 2 × t
SDRAM Clock Period = (t
(SDCKR)
DIVIDER
PMCTL
SDRAM
DIVIDE
BY 2
BUF
PCLK
PCLK
. See the peripheral
(PLLBP)
PMCTL
PCLK
CCLK
CCLK
SDCLK
) × SDCKR
CCLK