adsp-21478 Analog Devices, Inc., adsp-21478 Datasheet - Page 12

• Manufacturer Part Number: adsp-21478
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21478/ADSP-21479
FFT Accelerator
FFT accelerator implements radix-2 complex/real input, com-
plex output FFT with no core intervention.
FIR Accelerator
The FIR (finite impulse response) accelerator consists of a 1024
word coefficient memory, a 1024 word deep delay line for the
data, and four MAC units. A controller manages the accelerator.
The FIR accelerator runs at the peripheral clock frequency.
IIR Accelerator
The IIR (infinite impulse response) accelerator consists of a
1440 word coefficient memory for storage of biquad coeffi-
cients, a data memory for storing the intermediate data and one
MAC unit. A controller manages the accelerator. The IIR accel-
erator runs at the peripheral clock frequency.
Watch Dog Timer
The watch dog timer is used to supervise stability of the system
software. When used in this way, software reloads the watch dog
timer in a regular manner so that the downward counting timer
never expires. An expiring timer then indicates that system soft-
ware might be out of control.
The ADSP-2147x processors include a 32-bit watch dog timer
that can be used to implement a software watch dog function. A
software watch dog can improve system reliability by forcing the
processor to a known state through generation of a system reset,
if the timer expires before being reloaded by software. Software
initializes the count value of the timer, and then enables the
timer.
The watch dog timer resets both the core and the internal
peripherals. After an external reset, the WDT must be disabled
by default. Software must be able to determine if the watch dog
was the source of the hardware reset by interrogating a status bit
in the watch dog timer control register.
The WDT contains a software programmable Trip Counter reg-
ister that sets the number of times that the WDT can expire
before the WDTRSTO pin is continually asserted until the next
time hardware reset is applied. The trip counter is not cleared by
the WDT generated reset. This gives software the ability to
count the number of WDT generated resets using the CUR-
TRIPVAL field in the trip counter register.
Real-Time Clock
The real-time clock (RTC) provides a robust set of digital watch
features, including current time, stopwatch, and alarm. The
RTC is clocked by a 32.768 kHz crystal external to the SHARC
processor. Connect RTC pins RTXI and RTXO with external
components as shown in
The RTC peripheral has dedicated power supply pins so that it
can remain powered up and clocked even when the rest of the
processor is in a low power state. The RTC provides several pro-
grammable interrupt options, including interrupt per second,
minute, hour, or day clock ticks, interrupt on programmable
stopwatch countdown, or interrupt at a programmed alarm
time. An RTCLKOUT signal that operates at 1Hz is also pro-
vided for calibration.
Figure
3.
Rev. PrB | Page 12 of 70 | March 2010
The 32.768 kHz input clock frequency is divided down to a 1 Hz
signal by a prescaler. The counter function of the timer consists
of four counters: a 60-second counter, a 60-minute counter, a
24-hour counter, and an 32,768-day counter. When the alarm
interrupt is enabled, the alarm function generates an interrupt
when the output of the timer matches the programmed value in
the alarm control register. There are two alarms: The first alarm
is for a time of day. The second alarm is for a day and time of
that day.
The stopwatch function counts down from a programmed
value, with one-second resolution. When the stopwatch inter-
rupt is enabled and the counter underflows, an interrupt is
generated.
SYSTEM DESIGN
The following sections provide an introduction to system design
options and power supply issues.
Program Booting
The internal memory of the ADSP-2147x boots at system
power-up from an 8-bit EPROM via the external port, an SPI
master, or an SPI slave. Booting is determined by the boot con-
figuration (BOOT_CFG2–0) pins in
Table 8. Boot Mode Selection
1
The “Running Reset” feature is used to reset the processor core
and peripherals, but without resetting the PLL and SDRAM
controller, or performing a boot. The functionality of the RESE-
TOUT/RUNRSTIN pin has now been extended to also act as the
input for initiating a Running Reset. For more information, see
the ADSP-214xx SHARC Processor Hardware Reference.
BOOT_CFG2–0
000
001
010
011
100
1xx
The BOOT_CFG2 pin is not available on the 100-pin package.
Preliminary Technical Data
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.
C1
Figure 3. External Components for RTC
RTXI
1
Booting Mode
SPI Slave Boot
SPI Master Boot
AMI User Boot (for 8-bit Flash Boot)
Reserved
Reserved
Reserved
R1
X1
Table
C2
RTXO
8.