adsp-21478 Analog Devices, Inc., adsp-21478 Datasheet - Page 3

• Manufacturer Part Number: adsp-21478
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
GENERAL DESCRIPTION
The ADSP-21478/ADSP-21479/ SHARC
bers of the SIMD SHARC family of DSPs that feature Analog
Devices' Super Harvard Architecture. The processors are source
code compatible with the ADSP-2126x, ADSP-2136x, ADSP-
2137x, ADSP-2146x, and ADSP-2116x DSPs as well as with first
generation ADSP-2106x SHARC processors in SISD (single-
instruction, single-data) mode. These new processors are 32-
bit/40-bit floating point processors optimized for high perfor-
mance audio applications with its large on-chip SRAM, multiple
internal buses to eliminate I/O bottlenecks, and an innovative
digital applications interface (DAI).
Table 1
processors.
offerings.
Table 1. Processor Benchmarks
1
Table 2. ADSP-2147x Family Features
Benchmark Algorithm
1024 Point Complex FFT (Radix 4, With Reversal) 34.5 μs
FIR Filter (per Tap)
IIR Filter (per Biquad)
Matrix Multiply (Pipelined)
[3 × 3] × [3 × 1]
[4 × 4] × [4 × 1]
Divide (y/×)
Inverse Square Root
Assumes two files in multichannel SIMD mode
Feature
Frequency
RAM
ROM
Pulse-Width Modulation
AMI Interface with 16-bit
Support
SDRAM Memory Bus Width
Serial Ports
Direct DMA from SPORTs to
External Memory
FIR, IIR, FFT Accelerator
MLB Interface
Watch Dog Timer
Real-time Clock
Shift Register
IDP/PDAP
shows performance benchmarks for the ADSP-2147x
Table 2
1
shows the features of the individual product
1
ADSP-21478
Automotive Models Only
3M bits
®
processors are mem-
266 MHz
4 Units
16-bit
N/A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
8
ADSP-21479
Speed
(at 266 MHz)
1.88 ns
7.5 ns
16.91 ns
30.07 ns
13.1 ns
20.4 ns
Rev. PrB | Page 3 of 70 | March 2010
5M bits
Table 2. ADSP-2147x Family Features (Continued)
1
2
The diagram
up the ADSP-2147x processors. The core clock domain contains
the following features.
The block diagram of the ADSP-2147x
peripheral clock domain (also known as the I/O processor)
which contains the following features:
Available on the 100-lead package only.
The 100-lead packages of the ADSP-21478 and 21479 processors do not contain
Feature
UART
DAI (SRU)/DPI (SRU2)
S/PDIF Transceiver
SPI
TWI
SRC Performance
Thermal Diode
VISA Support
Package
an external port.
• Two processing elements (PEx, PEy), each of which com-
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting 2x64-bit data
• One periodic interval timer with pinout
• On-chip SRAM (up to 5M bit)
• JTAG test access port for emulation and boundary scan.
• IOD0 (peripheral DMA) and IOD1 (external port DMA)
• Peripheral and external port buses for core connection
• External port with an AMI and SDRAM controller
• 4 units for PWM control
• 1 MTM unit for internal-to-internal memory transfers
• Digital applications interface that includes four precision
prises an ALU, multiplier, shifter, and data register file
transfers between memory and the core at every core pro-
cessor cycle
The JTAG provides software debug through user break-
points which allows flexible exception handling.
buses for 32-bit data transfers
clock generators (PCG), an input data port (IDP/PDAP)
for serial and parallel interconnect, an S/PDIF
receiver/transmitter, four asynchronous sample rate con-
verters, eight serial ports, a flexible signal routing unit (DAI
SRU).
2
ADSP-21478/ADSP-21479
on Page 1
1
shows the two clock domains that make
ADSP-21478
196-Ball CSP_BGA
on Page 1
100-Lead LQFP
20/14 pins
–128 dB
Yes
Yes
1
1
2
1
ADSP-21479
also shows the