adsp-21478 Analog Devices, Inc., adsp-21478 Datasheet - Page 11

• Manufacturer Part Number: adsp-21478
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
In conjunction with the general-purpose timer functions, auto-
baud detection is supported.
Timers
The ADSP-2147x has a total of three timers: a core timer that
can generate periodic software interrupts and two general-pur-
pose timers that can generate periodic interrupts and be
independently set to operate in one of three modes:
The core timer can be configured to use FLAG3 as a timer
expired signal, and the general-purpose timers have one bidirec-
tional pin and four registers that implement its mode of
operation: a 6-bit configuration register, a 32-bit count register,
a 32-bit period register, and a 32-bit pulse width register. A sin-
gle control and status register enables or disables the general-
purpose timer.
2-Wire Interface Port (TWI)
The TWI is a bidirectional 2-wire, serial bus used to move 8-bit
data while maintaining compliance with the I
The TWI master incorporates the following features:
Shift Register
The shift register can be used as a serial to parallel data con-
verter. The shift register module consists of an 18-stage serial
shift register, 18-bit latch, and three-state output buffers. The
shift register and latch have separate clocks. Data is shifted into
the serial shift register on the positive-going transitions of the
shift register serial clock (SR_SCLK) input. The data in each
flip-flop is transferred to the respective latch on a positive-going
transition of the shift register latch clock (SR_LAT) input.
The shift register’s signals can be configured as follows.
• Support for data formats from 7 to 12 bits per frame.
• Both transmit and receive operations can be configured to
• Pulse waveform generation mode
• Pulse width count/capture mode
• External event watch dog mode
• 7-bit addressing
• Simultaneous master and slave operation on multiple
• Digital filtering and timed event processing
• 100 kbps and 400 kbps data rates
• Low interrupt rate
• The SR_SCLK can come from any of the SPORT0–7 SCLK
• The SR_LAT can come from any of SPORT0–7 Frame sync
• The SR_SDI input can from any of SPORT0–7 serial data
generate maskable interrupts to the processor.
device systems with support for multi master data
arbitration
outputs, PCGA/B clock, any of the DAI pins (1–8), and one
dedicated pin (SR_SCLK).
outputs, PCGA/B frame sync, any of the DAI pins (1–8),
and one dedicated pin (SR_LAT).
outputs, any of the DAI pins (1–8), and one dedicated pin
(SR_SDI).
2
C bus protocol.
Rev. PrB | Page 11 of 70 | March 2010
Note that the SR_SCLK, SR_LAT, and SR_SDI inputs must
come from same source except in the case of where SR_SCLK
comes from PCGA/B or SR_SCLK and SR_LAT come from
PCGA/B.
If SR_SCLK comes from PCGA/B, then SPORT0–7 will gener-
ate the SR_LAT and SR_SDI signals. If SR_SCLK and SR_LAT
come from PCGA/B, then SPORT0–7 will generate the SR_SDI
signal.
I/O PROCESSOR FEATURES
The I/O processor provides up to 65 channels of DMA as well as
an extensive set of peripherals.
DMA Controller
The processor’s on-chip DMA controller allows data transfers
without processor intervention. The DMA controller operates
independently and invisibly to the processor core, allowing
DMA operations to occur while the core is simultaneously exe-
cuting its program instructions. DMA transfers can occur
between the ADSP-2147x’s internal memory and its serial ports,
the SPI-compatible (serial peripheral interface) ports, the IDP
(input data port), the parallel data acquisition port (PDAP) or
the UART.
Up to 67 channels of DMA are available on the ADSP-2147x
processors as shown in
Programs can be downloaded to the ADSP-2147x using DMA
transfers. Other DMA features include interrupt generation
upon completion of DMA transfers, and DMA chaining for
automatic linked DMA transfers.
Table 7. DMA Channels
1
Delay Line DMA
The ADSP-2147x processor provides delay line DMA function-
ality. This allows processor reads and writes to external delay
line buffers (and hence to external memory) with limited core
interaction.
Scatter/Gather DMA
The ADSP-2147x processor provides scatter/gather DMA func-
tionality. This allows processor DMA reads/writes to/from non-
contingeous memory blocks.
Peripheral
SPORTs
PDAP
SPI
UART
External Port
Accelerators
Memory-to-Memory
MLB
Automotive models only.
1
ADSP-21478/ADSP-21479
Table
7.
16
8
2
2
2
2
2
31
DMA Channels