adsp-21478 Analog Devices, Inc., adsp-21478 Datasheet - Page 9

• Manufacturer Part Number: adsp-21478
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Asynchronous Memory Controller
The asynchronous memory controller, available on the
ADSP-21479 in the 196-ball CSP_BGA package, provides a con-
figurable interface for up to four separate banks of memory or
I/O devices. Each bank can be independently programmed with
different timing parameters, enabling connection to a wide vari-
ety of memory devices including SRAM, flash, and EPROM, as
well as I/O devices that interface with standard memory control
lines. Bank 0 occupies a 14M word window and banks 1, 2, and
3 occupy a 16M word window in the processor’s address space
but, if not fully populated, these windows are not made contigu-
ous by the memory controller logic.
External Port Throughput
The throughput for the external port, based on 133 MHz clock
and 16-bit data bus, is 88 M bytes/s for the AMI and 266 M
bytes/s for SDRAM.
MediaLB
The automotive models of the ADSP-2147x processors have an
MLB interface which allows the processor to function as a
media local bus device. It includes support for both 3-pin as well
as 5-pin media local bus protocols. It supports speeds up to 1024
FS (49.25 Mbits/sec, FS = 48.1 kHz) and up to 31 logical
channels, with up to 124 bytes of data per media local bus frame.
For a list of automotive products, see
Page
Pulse-Width Modulation
The PWM module is a flexible, programmable, PWM waveform
generator that can be programmed to generate the required
switching patterns for various applications related to motor and
engine control or audio power control. The PWM generator can
generate either center-aligned or edge-aligned PWM wave-
forms. In addition, it can generate complementary signals on
two outputs in paired mode or independent signals in non-
paired mode (applicable to a single group of four PWM
waveforms).
The entire PWM module has four groups of four PWM outputs
each. Therefore, this module generates 16 PWM outputs in
total. Each PWM group produces two pairs of PWM signals on
the four PWM outputs.
The PWM generator is capable of operating in two distinct
modes while generating center-aligned PWM waveforms: single
update mode or double update mode. In single update mode the
duty cycle values are programmable only once per PWM period.
This results in PWM patterns that are symmetrical about the
mid-point of the PWM period. In double update mode, a
second updating of the PWM registers is implemented at the
mid-point of the PWM period. In this mode, it is possible to
produce asymmetrical PWM patterns that produce lower har-
monic distortion in three-phase PWM inverters.
PWM signals can be mapped to the external port address lines
or to the DPI pins.
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Automotive Products on
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Digital Applications Interface (DAI)
The digital applications interface (DAI) provides the ability to
connect various peripherals to any of the DAI pins
(DAI_P20–1).
Programs make these connections using the signal routing unit
(SRU), shown in
The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be intercon-
nected under software control. This allows easy use of the DAI
associated peripherals for a much wider variety of applications
by using a larger set of algorithms than is possible with noncon-
figurable signal paths.
The DAI also includes eight serial ports, four precision clock
generators (PCG), S/PDIF transceiver, four ASRCs, and an
input data port (IDP). The IDP provides an additional input
path to the SHARC core, configurable as either eight channels
of serial data, or a single 20-bit wide synchronous parallel data
acquisition port. Each data channel has its own DMA channel
that is independent from the processor’s serial ports.
Serial Ports
The ADSP-2147x features eight synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices such as Analog Devices’
AD183x family of audio codecs, ADCs, and DACs. The serial
ports are made up of two data lines, a clock, and frame sync. The
data lines can be programmed to either transmit or receive and
each data line has a dedicated DMA channel.
Serial ports can support up to 16 transmit or 16 receive channels
of audio data when all eight SPORTs are enabled, or four full
duplex TDM streams of 128 channels per frame.
The serial ports operate at a maximum data rate of f
Serial port data can be automatically transferred to and from
on-chip memory/external memory via dedicated DMA chan-
nels. Each of the serial ports can work in conjunction with
another serial port to provide TDM support. One SPORT pro-
vides two transmit signals while the other SPORT provides the
two receive signals. The frame sync and clock are shared.
Serial ports operate in five modes:
Left-justified mode is a mode where in each frame sync cycle
two samples of data are transmitted/received—one sample on
the high segment of the frame sync, the other on the low seg-
ment of the frame sync. Programs have control over various
attributes of this mode.
Each of the serial ports supports the left-justified and I
cols (I
audio codecs, ADCs, and DACs such as the Analog Devices
AD183x family), with two data pins, allowing four left-justified
• Standard DSP serial mode
• Multichannel (TDM) mode
• I
• Packed I
• Left-justified mode
2
2
S mode
S is an industry-standard interface commonly used by
ADSP-21478/ADSP-21479
2
S mode
Figure
1.
PCLK
2
S proto-
/4.