adsp-21478 Analog Devices, Inc., adsp-21478 Datasheet - Page 14

• Manufacturer Part Number: adsp-21478
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21478/ADSP-21479
PIN FUNCTION DESCRIPTIONS
Table 9. Pin Descriptions
Name
ADDR
DATA
AMI_ACK
MS
AMI_RD
AMI_WR
FLAG0/IRQ0
FLAG1/IRQ1
FLAG2/IRQ2/MS2
FLAG3/TMREXP/MS3
The following symbols appear in the Type column of
O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic
levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors
cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26k–63kΩ.
The range of an ipd resistor can be between 31k–85kΩ.
In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins.
Not all pins are available in the 100-lead LQFP package. For more information, see
0–1
15–0
23–0
Type
I/O/T (ipu)
I/O/T (ipu)
I (ipu)
O/T (ipu)
O/T (ipu)
O/T (ipu)
I/O (ipu)
I/O (ipu)
I/O (ipu)
I/O (ipu)
State During/
After Reset
High-Z/driven
low (boot)
High-Z
High-Z
High-Z
High-Z
FLAG[0] INPUT
FLAG[1] INPUT
FLAG[2] INPUT
FLAG[3] INPUT
Rev. PrB | Page 14 of 70 | March 2010
Table
Description
External Address. The processor outputs addresses for external memory and
peripherals on these pins. The ADDR pins can be multiplexed to support the
external memory interface data (I/O), and FLAGS15–8 (I/O) and PWM (O). After
reset, all DATA pins are in EMIF mode and FLAG(0–3) pins are in FLAGS mode
(default). When configured in the IDP_PDAP_CTL register, IDP channel 0 scans the
ADDR
External Data. The data pins can be multiplexed to support the external memory
interface data (I/O), and FLAGS
Memory Acknowledge. External devices can deassert AMI_ACK (low) to add wait
states to an external memory access. AMI_ACK is used by I/O devices, memory
controllers, or other peripherals to hold off completion of an external memory
access.
Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the
corresponding banks of external memory on the AMI interface. The MS
are decoded memory address lines that change at the same time as the other
address lines. When no external memory access is occurring the MS
inactive; they are active however when a conditional memory access instruction
is executed, whether or not the condition is true.
The MS1 pin can be used in EPORT/FLASH boot mode. For more information on
processor booting, see the ADSP-214xx SHARC Processor Hardware Reference.
AMI Port Read Enable. AMI_RD is asserted whenever the processor reads a word
from external memory.
AMI Port Write Enable. AMI_WR is asserted when the processor writes a word to
external memory.
FLAG0/Interrupt Request0.
FLAG1/Interrupt Request1.
FLAG2/Interrupt Request2/Memory Select2. This pin is multiplexed with MS2
in the 196 BGA package only.
FLAG3/Timer Expired/Memory Select3. This pin is multiplexed with MS3 in the
196 BGA package only.
9: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,
23–4
pins for parallel input data.
Preliminary Technical Data
Table 2 on Page 3
7–0
(I/O).
and
Table 53 on Page
64.
1-0
lines are
1-0
lines