adsp-21478 Analog Devices, Inc., adsp-21478 Datasheet - Page 17

• Manufacturer Part Number: adsp-21478
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Table 9. Pin Descriptions (Continued)
1
Name
CLK_CFG
CLKIN
XTAL
RESET
RESETOUT/RUNRSTIN I/O (ipu)
BOOT_CFG
The following symbols appear in the Type column of
O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic
levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors
cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26k–63kΩ.
The range of an ipd resistor can be between 31k–85kΩ.
In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins.
Not all pins are available in the 100-lead LQFP package. For more information, see
The MLB pins are only available on the ADSP-21479W automotive processor.
1–0
2–0
Type
I
I
O
I
I
State During/
After Reset
Rev. PrB | Page 17 of 70 | March 2010
Table
Description
Core to CLKIN Ratio Control. These pins set the start up clock frequency.
Note that the operating frequency can be changed by programming the PLL
multiplier and divider in the PMCTL register at any time after the core comes out
of reset. The allowed values are:
00 = 8:1
01 = 32:1
10 = 16:1
11 = reserved
Local Clock In. Used in conjunction with XTAL. CLKIN is the clock input. It
configures the processors to use either its internal clock generator or an external
clock source. Connecting the necessary components to CLKIN and XTAL enables
the internal clock generator. Connecting the external clock to CLKIN while leaving
XTAL unconnected configures the processors to use the external clock source
such as an external clock oscillator. CLKIN may not be halted, changed, or
operated below the specified frequency.
Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external
crystal.
Processor Reset. Resets the processor to a known state. Upon deassertion, there
is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins
program execution from the hardware reset vector address. The RESET input must
be asserted (low) at power-up.
Reset Out/Running Reset In. The default setting on this pin is reset out. This pin
also has a second function as RUNRSTIN which is enabled by setting bit 0 of the
RUNRSTCTL register. For more information, see the ADSP-214xx SHARC Processor
Hardware Reference.
Boot Configuration Select. These pins select the boot mode for the processor.
The BOOT_CFG pins must be valid before RESET (hardware and software) is de-
asserted.
Note that the BOOT_CFG2 pin is not available on the 100-lead LQFP package.
9: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,
Table 2 on Page 3
ADSP-21478/ADSP-21479
and
Table 53 on Page
64.