adsp-21478 Analog Devices, Inc., adsp-21478 Datasheet - Page 59

• Manufacturer Part Number: adsp-21478
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
TWI Controller Timing
Table 48
interface. Input Signals (SCL, SDA) are routed to the
DPI_P14–1 pins using the SRU. Therefore, the timing specifica-
tions provided below are valid at the DPI_P14–1 pins.
Table 48. Characteristics of the SDA and SCL Bus Lines for F/S-Mode TWI Bus Devices
1
Parameter
f
t
t
t
t
t
t
t
t
t
All values referred to V
SCL
HDSTA
LOW
HIGH
SUSTA
HDDAT
SUDAT
SUSTO
BUF
SP
and
Figure 47
SCL Clock Frequency
Hold Time (repeated) Start Condition. After This
Period, the First Clock Pulse is Generated.
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated Start Condition
Data Hold Time for TWI-bus Devices
Data Setup Time
Setup Time for Stop Condition
Bus Free Time Between a Stop and Start Condition
Pulse Width of Spikes Suppressed By the Input Filter n/a
IHmin
DPI_P14–1
DPI_P14–1
provide timing information for the TWI
and V
SDA
SCL
ILmax
levels.
S
For more information, see Electrical Characteristics on page 20.
t
LOW
t
HDSTA
Figure 47. Fast and Standard Mode Timing on the TWI Bus
t
HDDAT
Rev. PrB | Page 59 of 70 | March 2010
t
HIGH
t
SUDAT
t
SUSTA
Min
0
4.0
4.7
4.0
4.7
0
250
4.0
4.7
Sr
Standard Mode
t
HDSTA
ADSP-21478/ADSP-21479
Max
100
n/a
t
1
SUSTO
t
SP
P
Min
0
0.6
1.3
0.6
0.6
0
100
0.6
1.3
0
t
BUF
Fast Mode
S
Max
400
50
Unit
kHz
μs
μs
μs
μs
μs
μs
μs
ns
ns